Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMV.X.S
RISC-V VMV.X.S Instruction Details
Instruction ManualR-typeMove vector element 0 into integer register rd.
Instruction Syntax
vmv.x.s rd, vs2
Operand Breakdown
vd: destination vector register group.
Source operand: from a vector register or integer register depending on the form.
VMV is an unmasked move/broadcast form; use VMERGE for selection under v0.
VVector Data MovementScalar-Vector Transfer
Instruction Behavior
VMV.X.S is a RISC-V V vector-scalar move instruction. It transfers an integer bit pattern between a scalar register and vector element 0 only; it is not a full-vector broadcast or a memory access.
Quick Understanding & Search Notes
VMV instructions move or broadcast data; they do not perform arithmetic or access memory.
This instruction is an unmasked form with no extra v0 execution mask; destination element coverage is defined by the instruction and current vl.
Move instructions preserve or extend source bit patterns according to the source type.
Use vmerge forms for masked selection rather than adding an ordinary execution mask to vmv.
Vector Execution Context
When reading VMV.X.S, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Init
Understand this scenario with real code like «vmv.x.s a0, v8».
Reduction Result
Understand this scenario with real code like «vmv.x.s a0, v8».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Operates even if vl=0—always reads element 0
Sign-extends if SEW<XLEN
FAQ
How does VMV.X.S handle masking?
It has no ordinary v0 execution mask; if a mask operand appears in the syntax, that operand is data, not an extra execution mask.