Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMV.X.S
RISC-V VMV.X.S Instruction Details
Instruction ManualOPMVXMove vector element 0 into integer register rd.
Instruction Syntax
vmv.x.s rd, vs2
Operand Breakdown
vd: destination vector register group.
Source operand: from a vector register or integer register depending on the form.
VMV is an unmasked move/broadcast form; use VMERGE for selection under v0.
VVector Data MovementVector-Scalar Transfer
Instruction Behavior
VMV.X.S is a RISC-V V vector-to-scalar move instruction. It transfers one integer bit pattern from element 0 of vs2 into integer register rd; it is not a full-vector broadcast or a memory access.
VMV.X.S Decode And Execute Animation
Starts from OP-V field decode, reads vector element 0, and writes an integer register using the SEW/XLEN rule.
Instruction input
Fixed vm and vs1 fields appear only in the encoding area below; they are not assembly syntax operands.
Execution context
Teaching context: LMUL=m1; VMV.X.S executes even when vl=0 or vstart>=vl.
funct6=010000vm=1vs2=01000vs1=00000funct3=110rd=01010opcode=1010111
Architectural visible state
x[10] <- 0xffffffffffffff80
Decode
The fixed OP-V fields identify the element-0-to-integer form: vm=1 and vs1=00000; masked vm=0 encodings are reserved.
Quick Understanding & Search Notes
VMV.X.S transfers only element 0 of vs2 to integer rd; it does not broadcast, access memory, or perform arithmetic. If rd is x0, the transferred result is discarded.
This instruction uses OPMVX encoding with fixed vm=1 and vs1=0; masked vm=0 encodings are reserved, and the assembly syntax has no v0.t execution mask.
It reads one SEW-wide element from vs2[0] into rd: with SEW>XLEN it transfers the low XLEN bits, with SEW<XLEN it sign-extends to XLEN bits, and with equal widths it transfers the bit pattern directly. LMUL and vector register groups do not affect this transfer.
VMV.X.S executes even when vstart>=vl or vl=0, unlike ordinary vector instructions that write body elements.
Vector Execution Context
When reading VMV.X.S, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Read vector element 0
Understand this scenario with real code like «vmv.x.s a0, v8».
Extract a scalar vector result
Understand this scenario with real code like «vmv.x.s a0, v8».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPMVX.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
It executes even when vl=0 or vstart>=vl and always reads element 0.
When SEW>XLEN it transfers the low XLEN bits; when SEW<XLEN it sign-extends element 0 to XLEN.
Masked vm=0 encodings are reserved; the syntax has no v0.t operand.
FAQ
Does VMV.X.S execute when vl is zero?
Yes. The specification states that VMV.X.S executes even when vstart>=vl or vl=0 and transfers vs2 element 0.