Does VMV.X.S execute when vl is zero?
Yes. The specification states that VMV.X.S executes even when vstart>=vl or vl=0 and transfers vs2 element 0.
VMV.X.S
RISC-V VMV.X.S Instruction Details
Instruction ManualOPMVVMove vector element 0 into integer register rd.
Instruction Syntax
vmv.x.s rd, vs2
Operand Breakdown
rd is an integer register; vs2 is a single vector register. LMUL is ignored.
32-bit OP-V: opcode=1010111, funct6=010000, funct3=010, vm=1; vs1=00000 is fixed; no v0.t operand.
Read only vs2[0]: SEW<XLEN sign-extends; SEW>XLEN takes low XLEN bits. Execute even with vl=0 or vstart≥vl; rd=x0 discards the write.
Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
VVector Data MovementVector-Scalar Transfer
Instruction Behavior
VMV.X.S is a RISC-V V vector-to-scalar move instruction. It transfers one integer bit pattern from element 0 of vs2 into integer register rd; it is not a full-vector broadcast or a memory access.
VMV.X.S Decode And Execute Animation
Starts from OP-V field decode, reads vector element 0, and writes an integer register using the SEW/XLEN rule.
Instruction input
Fixed vm and vs1 fields appear only in the encoding area below; they are not assembly syntax operands.
Execution context
Teaching context: VLEN=4096, selected SEW supported; LMUL and groups are ignored. VMV.X.S executes even when vl=0 or vstart>=vl.
funct6=010000vm=1vs2=01000vs1=00000funct3=010rd=01010opcode=1010111
Architectural visible state
Not read or written yet
Decode
The fixed OP-V fields identify the element-0-to-integer form: vm=1 and vs1=00000; masked vm=0 encodings are reserved.
Quick Understanding & Search Notes
VMV.X.S transfers only element 0 of vs2 to integer rd; it does not broadcast, access memory, or perform arithmetic. If rd is x0, the transferred result is discarded.
This instruction uses OPMVV encoding with fixed vm=1 and vs1=0; masked vm=0 encodings are reserved, and the assembly syntax has no v0.t execution mask.
It reads one SEW-wide element from vs2[0] into rd: with SEW>XLEN it transfers the low XLEN bits, with SEW<XLEN it sign-extends to XLEN bits, and with equal widths it transfers the bit pattern directly. LMUL and vector register groups do not affect this transfer.
VMV.X.S executes even when vstart>=vl or vl=0, unlike ordinary vector instructions that write body elements.
Vector Execution Context
rd is an integer register; vs2 is a single vector register. LMUL is ignored.
32-bit OP-V: opcode=1010111, funct6=010000, funct3=010, vm=1; vs1=00000 is fixed; no v0.t operand.
Read only vs2[0]: SEW<XLEN sign-extends; SEW>XLEN takes low XLEN bits. Execute even with vl=0 or vstart≥vl; rd=x0 discards the write.
Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
Common Usage Scenarios
Read vector element 0
Assume enabled V/VS, valid m1, VLEN≥128, initialized sources and vstart=0; XLEN=64, e8, v8[0]=0x80, vl=0 → x10=0xffffffffffffff80. Successful completion resets vstart to 0.
Extract a scalar vector result
Assume enabled V/VS, valid m1, VLEN≥128, initialized sources and vstart=0; XLEN=64, e8, v8[0]=0x80, vl=0 → x10=0xffffffffffffff80. Successful completion resets vstart to 0.
Pre-Use Checklist
Syntax Check
- rd is an integer register; vs2 is a single vector register. LMUL is ignored.
- 32-bit OP-V: opcode=1010111, funct6=010000, funct3=010, vm=1; vs1=00000 is fixed; no v0.t operand.
Semantic Check
- Read only vs2[0]: SEW<XLEN sign-extends; SEW>XLEN takes low XLEN bits. Execute even with vl=0 or vstart≥vl; rd=x0 discards the write.
- Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
Pitfalls / Common Confusions
It executes even when vl=0 or vstart>=vl and always reads element 0.
When SEW>XLEN it transfers the low XLEN bits; when SEW<XLEN it sign-extends element 0 to XLEN.
Masked vm=0 encodings are reserved; the syntax has no v0.t operand.