How does VMV.S.X handle masking?
It fixes vm=1 and vs2=0; vm=0 encodings are reserved and there is no v0.t. VMERGE selects sources under v0 for all body elements, so it is not equivalent to this single-element transfer.
VMV.S.X
RISC-V VMV.S.X Instruction Details
Instruction ManualOPMVXMove integer scalar x[rs1] into vector element 0.
Instruction Syntax
vmv.s.x vd, rs1
Operand Breakdown
vd is one vector register and rs1 is an integer x register; LMUL and register groups are ignored.
32-bit OP-V: opcode=1010111, funct6=010000, funct3=110, vm=1, vs2=00000; no v0.t operand.
When vstart<vl, write vd[0]: XLEN>SEW takes low bits, XLEN<SEW sign-extends, and x0 supplies zero. Other elements of the register follow vta.
vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart to 0. Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off.
VVector Data MovementScalar-Vector Transfer
Instruction Behavior
VMV.S.X is a RISC-V V integer scalar-to-vector-element move. It writes x[rs1] to vd[0], rather than broadcasting to a whole vector or accessing memory. When SEW is below XLEN it copies the low SEW bits; when SEW exceeds XLEN it sign-extends the scalar to SEW bits.
VMV.S.X Decode And Execute Animation
Starts from OP-V field decode and shows when an integer scalar writes vector element 0.
Instruction input
Fixed vm and vs2 fields appear only in the encoding area below; they are not assembly syntax operands.
Execution context
Teaching context: VLEN=4096 and support for the selected SEW. LMUL and register groups are ignored; only element 0 is shown. Steps are not processor cycles.
funct6=010000vm=1vs2=00000rs1=01010funct3=110vd=01000opcode=1010111
Architectural visible state
vd[0] <- 0xffffff80
When a write occurs, elements 1 through VLEN/SEW−1 of the single destination register follow vta: retain old values or permit all ones. With vstart≥vl the entire destination is unchanged. On successful completion, vstart resets to 0.
Decode
The fixed OP-V fields identify the scalar-to-element-0 form: vm=1 and vs2=00000; masked vm=0 encodings are reserved.
Quick Understanding & Search Notes
VMV.S.X writes an integer scalar to vd[0]. It performs no arithmetic, accesses no memory, and does not broadcast to the whole vector.
This instruction fixes vm=1 and vs2=0; its masked vm=0 encodings are reserved, and its syntax has no v0.t execution mask.
It writes only vd[0]: when SEW<XLEN it copies the low SEW bits of x[rs1], and when SEW>XLEN it sign-extends x[rs1] to SEW bits. LMUL and vector register groups do not affect this scalar-element transfer.
Elements after 0 follow the current tail agnostic/undisturbed policy. If vstart>=vl, including vl=0, the destination register is not updated.
Require V 1.0, supported SEW/LMUL, vtype.vill=0 and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. vstart≥vl (including vl=0) updates no destination elements, including tails.
Vector Execution Context
vd is one vector register and rs1 is an integer x register; LMUL and register groups are ignored.
32-bit OP-V: opcode=1010111, funct6=010000, funct3=110, vm=1, vs2=00000; no v0.t operand.
When vstart<vl, write vd[0]: XLEN>SEW takes low bits, XLEN<SEW sign-extends, and x0 supplies zero. Other elements of the register follow vta.
vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart to 0. Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off.
Common Usage Scenarios
Vector Init
Assume enabled V/VS, valid e8,m1, VLEN≥128, vl=4 and vstart=0; XLEN=64, x10=0x123456789abcdef0 → v8[0]=0xf0. Other elements of the single register follow vta. Tails are not assumed zero; vl=0 leaves the whole destination unchanged.
Element 0 Setup
Assume enabled V/VS, valid e8,m1, VLEN≥128, vl=4 and vstart=0; XLEN=64, x10=0x123456789abcdef0 → v8[0]=0xf0. Other elements of the single register follow vta. Tails are not assumed zero; vl=0 leaves the whole destination unchanged.
Pre-Use Checklist
Syntax Check
- vd is one vector register and rs1 is an integer x register; LMUL and register groups are ignored.
- 32-bit OP-V: opcode=1010111, funct6=010000, funct3=110, vm=1, vs2=00000; no v0.t operand.
Semantic Check
- When vstart<vl, write vd[0]: XLEN>SEW takes low bits, XLEN<SEW sign-extends, and x0 supplies zero. Other elements of the register follow vta.
- vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart to 0. Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off.
Pitfalls / Common Confusions
Writes only element 0; elements 1 and later follow the current tail policy.
When vstart >= vl, including vl=0, the destination vector register is not updated.
Unlike vmv.v.x, .s.x writes only element 0 while .v.x broadcasts to active body elements.