Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMV.S.X
RISC-V VMV.S.X Instruction Details
Instruction ManualOPMVXMove integer scalar x[rs1] into vector element 0.
Instruction Syntax
vmv.s.x vd, rs1
Operand Breakdown
vd: destination vector register group.
Source operand: from a vector register or integer register depending on the form.
VMV is an unmasked move/broadcast form; use VMERGE for selection under v0.
VVector Data MovementScalar-Vector Transfer
Instruction Behavior
VMV.S.X is a RISC-V V integer scalar-to-vector-element move. It writes x[rs1] to vd[0], rather than broadcasting to a whole vector or accessing memory. When SEW is below XLEN it copies the low SEW bits; when SEW exceeds XLEN it sign-extends the scalar to SEW bits.
VMV.S.X Decode And Execute Animation
Starts from OP-V field decode and shows when an integer scalar writes vector element 0.
Instruction input
Fixed vm and vs2 fields appear only in the encoding area below; they are not assembly syntax operands.
Execution context
Teaching context: LMUL=m1, VLMAX=64; only the architecturally defined element-0 state is shown.
funct6=010000vm=1vs2=00000rs1=01010funct3=110vd=01000opcode=1010111
Architectural visible state
vd[0] <- 0xffffff80
Elements 1 and later are tail elements and follow the current tail agnostic/undisturbed policy; they are not presented as fixed results. On successful completion, vstart resets to 0.
Decode
The fixed OP-V fields identify the scalar-to-element-0 form: vm=1 and vs2=00000; masked vm=0 encodings are reserved.
Quick Understanding & Search Notes
VMV.S.X writes an integer scalar to vd[0]. It performs no arithmetic, accesses no memory, and does not broadcast to the whole vector.
This instruction fixes vm=1 and vs2=0; its masked vm=0 encodings are reserved, and its syntax has no v0.t execution mask.
It writes only vd[0]: when SEW<XLEN it copies the low SEW bits of x[rs1], and when SEW>XLEN it sign-extends x[rs1] to SEW bits. LMUL and vector register groups do not affect this scalar-element transfer.
Elements after 0 follow the current tail agnostic/undisturbed policy. If vstart>=vl, including vl=0, the destination register is not updated.
Vector Execution Context
When reading VMV.S.X, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Init
Understand this scenario with real code like «vmv.s.x v8, a0».
Element 0 Setup
Understand this scenario with real code like «vmv.s.x v8, a0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPMVX.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Writes only element 0; elements 1 and later follow the current tail policy.
When vstart >= vl, including vl=0, the destination vector register is not updated.
Unlike vmv.v.x, .s.x writes only element 0 while .v.x broadcasts to active body elements.
FAQ
How does VMV.S.X handle masking?
It has no v0 execution mask: the encoding fixes vm=1 and vs2=0, while the vm=0 encodings are reserved. Use vmerge for selection under v0.