Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFMV.S.F
RISC-V VFMV.S.F Instruction Details
Instruction ManualV-type (OP-V / OPFVF)Copy scalar f register rs1 to vd element 0; remaining elements follow tail policy.
Instruction Syntax
vfmv.s.f vd, rs1
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsRegister Move
Related Search Terms
Instruction Behavior
VFMV.S.F copies floating-point scalar f[rs1] to element 0 of vd and ignores LMUL and vector register groups. Elements 1 through VLEN/SEW-1 are tail elements under the current tail-agnostic/undisturbed policy; if vstart >= vl, the destination register is not updated (therefore vl=0 does not update it). The masked vm=0 encodings are reserved. At SEW=16, this instruction is defined only when Zvfh is implemented.
VFMV.S.F Decode And Execute Animation
This model shows only architecturally visible register movement, fixed encoding, and vstart/vl conditions; it does not simulate NaNs, exception flags, or microarchitecture.
Instruction input
Execution context
FP stateFS enabledFS=Off raises illegal instruction
Encoding fields
funct6=010000 | vm=1 | vs2=00000 (v0) | vs1/rs1=ft0 | funct3=101 | opcode=1010111
hex: 0x42005257
The vm=0 encodings of both element-0 FP scalar moves are reserved.
Architectural data path
f[ft0] -> v4[0]
Step 1 / 4
VFMV.S.F uses OP-V; vm is fixed to 1, and the masked vm=0 encodings are reserved.
Quick Understanding & Search Notes
VFMV.S.F places one FP scalar into element 0 of a vector register.
Unlike VFMV.V.F, it does not copy the scalar to all active elements.
Vector Execution Context
When reading VFMV.S.F, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Reduction Init
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmv.s.f v1, ft0 # v1[0] = ft0, other elements follow tail policy».
Scalar to Element 0
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmv.s.f v1, ft0 # v1[0] = ft0, other elements follow tail policy».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type (OP-V / OPFVF).
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only element 0 is explicitly written; use VFMV.V.F for broadcast.
When vstart >= vl, including vl=0, the destination is not updated; otherwise elements after 0 follow the tail policy.
FAQ
Is VFMV.S.F a broadcast?
No. It writes only vd[0]; the broadcast form is VFMV.V.F.