Is VFMV.S.F a broadcast?
No. It writes only vd[0]; the broadcast form is VFMV.V.F.
VFMV.S.F
RISC-V VFMV.S.F Instruction Details
Instruction ManualV-type (OP-V / OPFVF)Copy scalar f register rs1 to vd element 0; remaining elements follow tail policy.
Instruction Syntax
vfmv.s.f vd, rs1
Operand Breakdown
Syntax is vd, rs1. vd is one vector register and rs1 selects FP f0–f31 (or an ABI name). It copies to element 0, without broadcasting.
funct6=010000, funct3=101, vs2=00000, vm=1; vm=0 is reserved and there is no execution-mask operand.
LMUL and vector register groups are ignored. At vstart≥vl (including vl=0) the destination is unchanged; otherwise vd[0] is written and elements 1 and above follow the tail policy. Successful execution resets vstart=0.
At FLEN>SEW the scalar must be validly NaN-boxed or is read as canonical NaN; FLEN<SEW is reserved. V supports FP32/64; this move at SEW=16 requires Zvfh. The animation fixes SEW=FLEN=64 and assumes support for the selected vstart.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
VVector OperationsRegister Move
Related Search Terms
Instruction Behavior
VFMV.S.F copies floating-point scalar f[rs1] to element 0 of vd and ignores LMUL and vector register groups. Elements 1 through VLEN/SEW-1 are tail elements under the current tail-agnostic/undisturbed policy; if vstart >= vl, the destination register is not updated (therefore vl=0 does not update it). The masked vm=0 encodings are reserved. At SEW=16, this instruction is defined only when Zvfh is implemented.
VFMV.S.F Decode And Execute Animation
The teaching context fixes SEW=FLEN=64, VLEN=4096, valid vtype, frm=RNE, enabled VS/FS, and support for the selected vstart. Inputs are represented as finite binary64 before copying their bits. The model shows movement, encoding, and vstart/vl conditions, without simulating NaNs, exception flags, or microarchitecture.
Instruction input
Execution context
FP stateFS enabledFS=Off raises illegal instruction
Encoding fields
funct6=010000 | vm=1 | vs2=00000 (v0) | vs1/rs1=ft0 | funct3=101 | vd/rd=00100 | opcode=1010111
hex: 0x42005257
The vm=0 encodings of both element-0 FP scalar moves are reserved.
Architectural data path
f[ft0] -> v4[0]
Step 1 / 4
VFMV.S.F uses OP-V; vm is fixed to 1, and the masked vm=0 encodings are reserved.
Quick Understanding & Search Notes
VFMV.S.F places one FP scalar into element 0 of a vector register.
Unlike VFMV.V.F, it does not copy the scalar to all active elements.
Vector Execution Context
Syntax is vd, rs1. vd is one vector register and rs1 selects FP f0–f31 (or an ABI name). It copies to element 0, without broadcasting.
funct6=010000, funct3=101, vs2=00000, vm=1; vm=0 is reserved and there is no execution-mask operand.
LMUL and vector register groups are ignored. At vstart≥vl (including vl=0) the destination is unchanged; otherwise vd[0] is written and elements 1 and above follow the tail policy. Successful execution resets vstart=0.
At FLEN>SEW the scalar must be validly NaN-boxed or is read as canonical NaN; FLEN<SEW is reserved. V supports FP32/64; this move at SEW=16 requires Zvfh. The animation fixes SEW=FLEN=64 and assumes support for the selected vstart.
Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Common Usage Scenarios
Reduction Init
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. ft0 is validly NaN-boxed at FLEN=64. The example is unmasked: ft0=1.5 → v1[0]=1.5. Elements 1 and above are tail; ta does not guarantee zeros.
Scalar to Element 0
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, FLEN=64, VLMAX≥4, a0=4, and vstart=0 after vsetvli. ft0 is validly NaN-boxed at FLEN=64. The example is unmasked: ft0=1.5 → v1[0]=1.5. Elements 1 and above are tail; ta does not guarantee zeros.
Pre-Use Checklist
Syntax Check
- Syntax is vd, rs1. vd is one vector register and rs1 selects FP f0–f31 (or an ABI name). It copies to element 0, without broadcasting.
- funct6=010000, funct3=101, vs2=00000, vm=1; vm=0 is reserved and there is no execution-mask operand.
Semantic Check
- LMUL and vector register groups are ignored. At vstart≥vl (including vl=0) the destination is unchanged; otherwise vd[0] is written and elements 1 and above follow the tail policy. Successful execution resets vstart=0.
- At FLEN>SEW the scalar must be validly NaN-boxed or is read as canonical NaN; FLEN<SEW is reserved. V supports FP32/64; this move at SEW=16 requires Zvfh. The animation fixes SEW=FLEN=64 and assumes support for the selected vstart.
- Require valid vtype, supported FP widths and matching scalar FP extensions, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or for operations that do not round; vxrm does not control FP operations.
Pitfalls / Common Confusions
Only element 0 is explicitly written; use VFMV.V.F for broadcast.
When vstart >= vl, including vl=0, the destination is not updated; otherwise elements after 0 follow the tail policy.