Do these instructions use vxrm?
No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFWMUL.VF
RISC-V VFWMUL.VF Instruction Details
Instruction ManualR-typeMultiply narrow floating-point operands and write the widened 2*SEW result to vd.
Instruction Syntax
vfwmul.vf vd, rs1, vs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector Multiply-AddFloating-Point
Instruction Behavior
VFWMUL.VF is widening floating-point multiply, not an accumulate instruction. f[rs1] is multiplied by vs2[i]. The result is written to vd at 2*SEW width. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Quick Understanding & Search Notes
VFWMUL.VF is only widening multiply: narrow inputs are multiplied and the wide result is written to vd.
There is no old-vd accumulation term; that is the main difference from VFWMACC/VFWMSAC.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, and fixed-point vxrm does not control these instructions.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Common Usage Scenarios
High-Precision Matrix
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vfwmul.vf v2, ft0, v4».
Mixed-Precision ML
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vfwmul.vf v2, ft0, v4».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vd is a widened destination, not an accumulator; use VFWMACC/VFWMSAC forms for widening fused accumulation.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.