Does VFWMUL.VF use old vd as an accumulator?
It does not use old vd as an accumulator. Active elements receive double-width products; legal narrow-source/wide-destination overlap still reads the overlapping source values.
VFWMUL.VF
RISC-V VFWMUL.VF Instruction Details
Instruction ManualOPFVFMultiply vs2[i] by scalar f[rs1] and write the 2*SEW-wide result to vd[i].
Instruction Syntax
vfwmul.vf vd, vs2, rs1, vm
Operand Breakdown
Syntax: vfwmul.vf vd, vs2, rs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111000. Old vd is not an accumulator.
Narrow vector sources use EEW=SEW, EMUL=LMUL; vd uses EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. Equal narrow sources read equal initial values.
Each active element computes (f[rs1] * vs2[i]), producing a double-width product. The real instruction uses dynamic frm, not vxrm. rs1 selects an f register; when FLEN>SEW an invalid NaN box supplies canonical NaN. FLEN<SEW encodings are reserved.
Omitting v0.t means vm=1; including it means vm=0. Only elements with vstart≤i<vl and an enabled mask execute and accrue FP exceptions to fflags. A masked destination cannot include v0; one register cannot be read as both an EEW=1 mask and different-EEW data source.
Prestart elements do not update or raise exceptions; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, RNE, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, or fflags.
VVector Multiply-AddFloating-Point
Extension condition: V 1.0 on RV32/RV64, with supported FP formats and vtype and enabled VS/FS. Standard V supports the SEW=32-to-binary64 path shown here; this does not imply a supported binary128 result at SEW=64.
Instruction Behavior
VFWMUL.VF performs lane-wise widening FP multiplication: each active element computes vs2[i] x f[rs1] and writes a 2*SEW-wide result to vd[i]. It does not read old vd as an accumulator; the mask, vl, and current vtype determine which elements execute.
VFWMUL.VF Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise widening FP multiplication: SEW=32 sources are widened before their product is written as a 2*SEW=64 result.
Instruction input
vfwmul.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
dest EEWdestination element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xe0855257
31..26
25
24..20
19..15
14..12
11..7
6..0
111000
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 * 1.5 -> 1.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 * 1.5
1.5
i=1active
1.5 * 1.5
2.25
i=2skip
v0.t=0, not executed
--
i=3active
2.5 * 1.5
3.75
i=4active
-3 * 1.5
-4.5
i=5active
3.5 * 1.5
5.25
i=6skip
v0.t=0, not executed
--
i=7active
4.5 * 1.5
6.75
This model fixes SEW=32, LMUL=m1, VLEN=4096, VLMAX=128, vstart=0, valid vtype, enabled VS/FS, and ta/ma. Multipliers are first represented as binary32, with binary64 results. Old vd is not an accumulator; a narrow source may overlap only the high end of the two-register destination group. Legal different-EEW overlap forces mask/tail agnostic. The scalar is read at FLEN=64 with valid NaN-boxing assumed. Inactive/tail elements have no definite displayed values; VL=0 updates no destination elements. NaNs, infinities, fflags, and microarchitectural cycles are outside this model; the real instruction uses dynamic frm, with invalid frm use reserved even at VL=0.
Quick Understanding & Search Notes
VFWMUL.VF multiplies each active vs2[i] by f[rs1] and writes the widened 2*SEW result to vd[i]; there is no old-vd accumulation term.
The official syntax is vfwmul.vf vd, vs2, rs1, vm: vs2 is the vector source and the FP register numbered by rs1 supplies the scalar source.
This is a 2*SEW = SEW x SEW widening multiply; each vd element is twice the width of a source element.
There is no old-vd accumulation term; compare the separate VFWMACC/VFWMSAC semantics when a widening fused accumulation is needed.
Only elements with vstart≤i<vl that are not disabled by the execution mask execute; vm=0 uses v0 as the per-element execution mask.
The OP-V encoding uses opcode=1010111, funct3=101 (OPFVF), and funct6=111000.
Narrow sources use EEW=SEW and EMUL=LMUL; the wide destination uses EEW=2*SEW and EMUL=2*LMUL. Encodings requiring EMUL>8 are reserved.
Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic.
Active elements satisfy vstart≤i<vl with the mask enabled; vl=0 or vstart≥vl updates no destination elements, including tails. ta/ma does not guarantee zeros; successful execution resets vstart=0.
The real instruction uses dynamic frm; invalid frm use is reserved even at vl=0. Only active-element FP exceptions accrue in fflags.
Vector Execution Context
Syntax: vfwmul.vf vd, vs2, rs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111000. Old vd is not an accumulator.
Narrow vector sources use EEW=SEW, EMUL=LMUL; vd uses EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. Equal narrow sources read equal initial values.
Each active element computes (f[rs1] * vs2[i]), producing a double-width product. The real instruction uses dynamic frm, not vxrm. rs1 selects an f register; when FLEN>SEW an invalid NaN box supplies canonical NaN. FLEN<SEW encodings are reserved.
Omitting v0.t means vm=1; including it means vm=0. Only elements with vstart≤i<vl and an enabled mask execute and accrue FP exceptions to fflags. A masked destination cannot include v0; one register cannot be read as both an EEW=1 mask and different-EEW data source.
Prestart elements do not update or raise exceptions; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, RNE, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, or fflags.
Common Usage Scenarios
binary32 multipliers with binary64 products
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. The FP scalar is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v4(binary32)=[2,4,-2,0], ft0=1.5 → v2/v3(binary64)=[3,6,-3,0]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwmul.vf vd, vs2, rs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111000. Old vd is not an accumulator.
- Narrow vector sources use EEW=SEW, EMUL=LMUL; vd uses EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic. Equal narrow sources read equal initial values.
Semantic Check
- Each active element computes (f[rs1] * vs2[i]), producing a double-width product. The real instruction uses dynamic frm, not vxrm. rs1 selects an f register; when FLEN>SEW an invalid NaN box supplies canonical NaN. FLEN<SEW encodings are reserved.
- Omitting v0.t means vm=1; including it means vm=0. Only elements with vstart≤i<vl and an enabled mask execute and accrue FP exceptions to fflags. A masked destination cannot include v0; one register cannot be read as both an EEW=1 mask and different-EEW data source.
- Prestart elements do not update or raise exceptions; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- V 1.0 supports RV32/RV64 and depends on F/D. Require supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, RNE, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, or fflags.
Pitfalls / Common Confusions
Assembly order is vd, vs2, rs1, vm; rs1 names a scalar FP register, not a vector source register.
vd receives a 2*SEW-wide result and old vd is not an accumulator; legal wide destination groups and overlap follow the current vtype.