Do these instructions use vxrm?
No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFWMACC.VV
RISC-V VFWMACC.VV Instruction Details
Instruction ManualR-typeWidening FP FMA: wide_product = widen(vs1[i] * vs2[i]), vd[i] = +(wide_product) + vd[i].
Instruction Syntax
vfwmacc.vv vd, vs1, vs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector Multiply-AddFloating-Point
Instruction Behavior
VFWMACC.VV performs widening floating-point fused multiply-add/subtract. Two narrow vector source elements are multiplied. The product is widened to 2*SEW and combined with wide vd using vd[i] = +(wide_product) + vd[i], fused with one rounding. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Quick Understanding & Search Notes
VFWMACC.VV forms a wide product from narrow inputs and fuses it with wide vd using vd[i] = +(wide_product) + vd[i].
Widening FMA writes 2*SEW destination elements, so register-group use changes with EMUL.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, and fixed-point vxrm does not control these instructions.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Common Usage Scenarios
High-Precision Matrix
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vfwmacc.vv v2, v4, v6».
Mixed-Precision ML
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vfwmacc.vv v2, v4, v6».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Use the formula wide_product = widen(vs1[i] * vs2[i]); vd[i] = +(wide_product) + vd[i].
vd is a 2*SEW-wide read/write destination; do not confuse widening FMA with plain VFWMUL multiply.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.