Is vd output-only?
No. In the official definition, vd is the 2*SEW-wide addend and is overwritten by the final result; the animation exposes it as an editable accumulator input.
VFWMACC.VF
RISC-V VFWMACC.VF Instruction Details
Instruction ManualOPFVFwidening fused multiply-accumulate: f[rs1] and vs2[i] are SEW-wide multipliers, while wide vd[i] is the 2*SEW addend and result; (f[rs1] * vs2[i]) + vd[i].
Instruction Syntax
vfwmacc.vf vd, rs1, vs2, vm
Operand Breakdown
Syntax: vfwmacc.vf vd, rs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111100. Read the old wide vd addend before overwriting it.
Narrow vector sources have EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. vd is also a wide source, so narrow multipliers cannot share registers with its group. Equal narrow sources read equal initial values.
Each active element computes (f[rs1] * vs2[i]) + old vd[i]. The product is not separately rounded; dynamic frm rounds only the final wide result. rs1 selects an FP f register; an invalid NaN box supplies canonical NaN when FLEN>SEW, and FLEN<SEW is reserved.
Omitting v0.t means vm=1; including it means vm=0. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. A masked destination cannot include v0; one register cannot be read as data and mask sources with different EEWs.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without frm-based rounding or at vl=0; invalid frm use is reserved. vxrm is not used. This finite teaching model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and ta/ma; it is not a complete FP simulator.
VVector Multiply-AddFloating-Point
Instruction Behavior
VFWMACC.VF overwrites the wide addend under the official RVV semantics: f[rs1] and vs2[i] are SEW-wide multipliers, while vd[i] is both the 2*SEW-wide input and result. Each active element evaluates (f[rs1] * vs2[i]) + vd[i] with one fused rounding to the wide result format. With vm=0, v0.t controls lane execution; this page's interactive example fixes a checkable SEW=32-to-binary64 path.
VFWMACC.VF Decode And Execute Animation
Decode the OP-V encoding and execute widening fused multiply-add lane by lane: two SEW=32 multipliers and the 2*SEW=64 wide vd[i] produce one binary64 fused result; the second multiplier is scalar f[rs1].
Instruction input
vfwmacc.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
acc/dest EEWvd is the FP64 wide addend and result
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xf0855257
31..26
25
24..20
19..15
14..12
11..7
6..0
111100
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma(1, 1.5, 0.5) -> 2
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma(1, 1.5, 0.5)
2
i=1active
fma(1.5, 1.5, -1)
1.25
i=2skip
v0.t=0, not executed
--
i=3active
fma(2.5, 1.5, -2.5)
1.25
i=4active
fma(-3, 1.5, 4)
-0.5
i=5active
fma(3.5, 1.5, -4.5)
0.75
i=6skip
v0.t=0, not executed
--
i=7active
fma(4.5, 1.5, -8.5)
-1.75
This model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, valid vtype, enabled VS/FS, and ta/ma. Narrow multipliers are represented as binary32 and old vd as binary64; the fused operation rounds only once to binary64 (RNE). The scalar is read at FLEN=64 with valid NaN-boxing assumed. The wide vd source group cannot share registers with narrow multipliers. Inactive/tail elements have no definite displayed values; VL=0 updates no destination elements. NaNs, infinities, fflags, and microarchitectural cycles are outside this model; the real instruction still handles these conditions by the official FP rules.
Quick Understanding & Search Notes
Read f[rs1] and vs2[i] as SEW-wide multipliers, then fuse them with wide vd[i] as (f[rs1] * vs2[i]) + vd[i]; vd[i] is overwritten by the result.
The official widening FMA definition overwrites the wide addend: multiplier inputs are SEW, while the vd addend and destination elements are 2*SEW.
This instruction's per-element formula is vd[i] = (f[rs1] * vs2[i]) + vd[i].
The encoding is opcode=1010111 (OP-V), funct3=101 (OPFVF), funct6=111100.
Only active elements within vl execute; with vm=0, v0.t decides whether a lane executes.
FP arithmetic uses frm; this interactive animation shows an exact fused calculation for finite binary32-to-binary64 inputs under RNE.
Vector Execution Context
Syntax: vfwmacc.vf vd, rs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111100. Read the old wide vd addend before overwriting it.
Narrow vector sources have EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. vd is also a wide source, so narrow multipliers cannot share registers with its group. Equal narrow sources read equal initial values.
Each active element computes (f[rs1] * vs2[i]) + old vd[i]. The product is not separately rounded; dynamic frm rounds only the final wide result. rs1 selects an FP f register; an invalid NaN box supplies canonical NaN when FLEN>SEW, and FLEN<SEW is reserved.
Omitting v0.t means vm=1; including it means vm=0. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. A masked destination cannot include v0; one register cannot be read as data and mask sources with different EEWs.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without frm-based rounding or at vl=0; invalid frm use is reserved. vxrm is not used. This finite teaching model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and ta/ma; it is not a complete FP simulator.
Common Usage Scenarios
SEW multipliers with a 2*SEW addend
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. fa0 is a validly NaN-boxed binary32 value at FLEN=64. Omitting v0.t makes this unmasked: old v4/v5(binary64)=[1,2,-3,4], fa0=1.5, v8=[2,4,-2,0] → v4/v5=[4,8,-6,4]. Tails follow ta without guaranteed zeros.
active-element fused multiply-add
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. fa0 is a validly NaN-boxed binary32 value at FLEN=64. Omitting v0.t makes this unmasked: old v4/v5(binary64)=[1,2,-3,4], fa0=1.5, v8=[2,4,-2,0] → v4/v5=[4,8,-6,4]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwmacc.vf vd, rs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111100. Read the old wide vd addend before overwriting it.
- Narrow vector sources have EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. vd is also a wide source, so narrow multipliers cannot share registers with its group. Equal narrow sources read equal initial values.
Semantic Check
- Each active element computes (f[rs1] * vs2[i]) + old vd[i]. The product is not separately rounded; dynamic frm rounds only the final wide result. rs1 selects an FP f register; an invalid NaN box supplies canonical NaN when FLEN>SEW, and FLEN<SEW is reserved.
- Omitting v0.t means vm=1; including it means vm=0. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. A masked destination cannot include v0; one register cannot be read as data and mask sources with different EEWs.
- Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without frm-based rounding or at vl=0; invalid frm use is reserved. vxrm is not used. This finite teaching model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and ta/ma; it is not a complete FP simulator.
Pitfalls / Common Confusions
The official formula is vd[i] = (f[rs1] * vs2[i]) + vd[i]; vd is the wide addend overwritten by the result.
The two multipliers are SEW wide and vd is 2*SEW wide; do not treat this as single-width FMA or plain VFWMUL.
FMA rounds only at the final wide result; do not model it as a rounded product followed by addition.
vd is also a wide source; narrow multipliers cannot share registers with the wide vd group, since that would read one register at different EEWs in a single instruction.