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VFWMUL.VV

RISC-V VFWMUL.VV Instruction Details

Instruction ManualR-type

Multiply narrow floating-point operands and write the widened 2*SEW result to vd.

Instruction Syntax

vfwmul.vv vd, vs1, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector Multiply-AddFloating-Point
Related Search Terms
VFWMUL.VV instructionRISC-V VFWMUL.VVvfwmul.vv syntaxvfwmul.vv RVVwidening multiply2*SEW

Instruction Behavior

VFWMUL.VV is widening floating-point multiply, not an accumulate instruction. vs1[i] is multiplied by vs2[i]. The result is written to vd at 2*SEW width. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.

Quick Understanding & Search Notes

VFWMUL.VV is only widening multiply: narrow inputs are multiplied and the wide result is written to vd.

There is no old-vd accumulation term; that is the main difference from VFWMACC/VFWMSAC.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point arithmetic and conversions follow RVV FP rules; ordinary FP rounding comes from frm, and fixed-point vxrm does not control these instructions.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFWMUL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

High-Precision Matrix

Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vfwmul.vv v2, v4, v6».

Mixed-Precision ML

Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vfwmul.vv v2, v4, v6».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

vd is a widened destination, not an accumulator; use VFWMACC/VFWMSAC forms for widening fused accumulation.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.

FAQ

Do these instructions use vxrm?

No. FP arithmetic and conversions use frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.