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VFWMUL.VV

RISC-V VFWMUL.VV Instruction Details

Instruction ManualOPFVV

Multiply vs2[i] by same-lane vs1[i] and write the 2*SEW-wide result to vd[i].

Instruction Syntax

vfwmul.vv vd, vs2, vs1, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VVector Multiply-AddFloating-Point

Related Search Terms

VFWMUL.VV instruction RISC-V VFWMUL.VV vfwmul.vv syntax vfwmul.vv RVV vector widening multiply OPFVV encoding 2*SEW result

Instruction Behavior

VFWMUL.VV performs lane-wise widening FP multiplication: each active element computes vs2[i] x vs1[i] and writes a 2*SEW-wide result to vd[i]. It does not read old vd as an accumulator; the mask, vl, and current vtype determine which elements execute.

VFWMUL.VV Decode And Execute Animation

Decode the OP-V encoding and execute lane-wise widening FP multiplication: SEW=32 sources are widened before their product is written as a 2*SEW=64 result.

Instruction input

vfwmul.vv

vdUse v0-v31vs2Use v0-v31vs1Use v0-v31vmexecution mask control

Execution context

VLSEW

LMULm1fixed register-group multiplier

VLEN4096fixed vector-register length (bits)

VLMAX128maximum element count at m1

vstart0prestart elements are outside this animation

frmRNEfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm

FP stateFS enabledFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled

dest EEW64destination element width

vta/vmata, matail/inactive policy

opcode1010111OP-V major opcode

vs2 elementsComma-separated finite values, count must equal VL, representable as finite binary32vs1 elementsComma-separated finite values, count must equal VL, representable as finite binary32v0 mask bits0/1 string, length must equal VL

Encoding fields

0xe0861257

31..26

24..20

19..15

14..12

11..7

6..0

111000

funct6

01000

vs2

01100

vs1

001

funct3

00100

1010111

OP-V

Execution data path

lane 0: 1 * 0.5 -> 0.5

This lane follows the current-step highlight; the remaining lane results appear below.

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

1 * 0.5

0.5

i=1active

1.5 * 1

1.5

i=2skip

v0.t=0, not executed

i=3active

2.5 * 2

i=4active

-3 * 2.5

-7.5

i=5active

3.5 * 3

10.5

i=6skip

v0.t=0, not executed

i=7active

4.5 * 4

In the fixed VLEN=4096, LMUL=m1, vstart=0 teaching context, source elements are represented as SEW=32 / binary32, widened exactly to binary64, then multiplication executes in binary64 before writing the 2*SEW=64 result. This animation uses RNE as a checkable demo mode; NaNs, infinities, and exception flags remain governed by the official RVV FP rules.

Quick Understanding & Search Notes

VFWMUL.VV multiplies each active vs2[i] by vs1[i] and writes the widened 2*SEW result to vd[i]; there is no old-vd accumulation term.

The official syntax is vfwmul.vv vd, vs2, vs1, vm: each active element uses same-lane vs2[i] and vs1[i].

This is a 2*SEW = SEW x SEW widening multiply; each vd element is twice the width of a source element.

There is no old-vd accumulation term; compare the separate VFWMACC/VFWMSAC semantics when a widening fused accumulation is needed.

Only elements within vl that are not disabled by the execution mask execute; vm=0 uses v0 as the per-element execution mask.

The OP-V encoding uses opcode=1010111, funct3=001 (OPFVV), and funct6=111000.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFWMUL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

High-Precision Matrix

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwmul.vv v2, v4, v6 # vd[i] = widen(vs2[i]) * widen(vs1[i])».

Mixed-Precision ML

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwmul.vv v2, v4, v6 # vd[i] = widen(vs2[i]) * widen(vs1[i])».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is OPFVV.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Assembly order is vd, vs2, vs1, vm; the two vector sources are paired at the same element index.

vd receives a 2*SEW-wide result and old vd is not an accumulator; legal wide destination groups and overlap follow the current vtype.

FAQ

Does VFWMUL.VV read old vd?

No. It writes the product of vs2[i] and vs1[i] to widened vd[i]; an old-vd accumulator input belongs to widening fused multiply-accumulate semantics.