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VFRSUB.VF

RISC-V VFRSUB.VF Instruction Details

Instruction ManualR-type

VFRSUB.VF performs vector-scalar FP reverse subtract on active elements within VL: vd[i] = f[rs1] - vs2[i].

Instruction Syntax

vfrsub.vf vd, vs2, rs1, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VZvfhVector OperationsFloating-Point

Related Search Terms

VFRSUB.VF instruction RISC-V VFRSUB.VF vfrsub.vf syntax vfrsub.vf encoding RVV FP reverse subtraction vfrsub.vf mask execution vfrsub.vf frm rounding

Instruction Behavior

VFRSUB.VF is an RVV single-width floating-point reverse subtraction instruction with syntax vfrsub.vf vd, vs2, rs1, vm. Each active element uses the current SEW FP format to execute vd[i] = f[rs1] - vs2[i]; It subtracts the vector element from the scalar; it is not a reduction or an integer reverse subtract. With vm=0, v0.t controls active elements; with vm=1, execution is unmasked. Rounding mode and exception flags follow the official RVV floating-point rules, and fixed-point vxrm does not control these instructions.

VFRSUB.VF Decode And Execute Animation

Decode the OP-V encoding and execute reverse FP subtraction lane by lane: each active lane computes f[rs1] - vs2[i].

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Instruction input

vfrsub.vf

vdUse v0-v31vs2Use v0-v31rs1FP register f0-f31/ABIvmexecution mask control

Execution context

VLSEW

frm

RNE

demo dynamic rounding mode

vta/vma

ta, ma

tail/inactive policy

opcode

1010111

OP-V major opcode

vs2 elementsComma-separated finite values, count must equal VL, representable as finite binary32f[rs1]finite FP demo value, representable as finite binary32v0 mask bits0/1 string, length must equal VL

Encoding fields

0x9c855257

31..26

24..20

19..15

14..12

11..7

6..0

100111

funct6

01000

vs2

01010

rs1

101

funct3

00100

1010111

OP-V

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

1.5 - 1

0.5

i=1active

1.5 - 1.5

i=2skip

v0.t=0, not executed

i=3active

1.5 - 2.5

-1

i=4active

1.5 - -3

4.5

i=5active

1.5 - 3.5

-2

i=6skip

v0.t=0, not executed

i=7active

1.5 - 4.5

-3

The animation quantizes source values and results for the current SEW under the RNE demo mode: SEW=32 uses binary32 and SEW=64 uses binary64. NaN, infinity, and exception flags still follow the official RVV FP rules and are not expanded here as a full FP exception simulator.

Quick Understanding & Search Notes

VFRSUB.VF is best understood through OP-V encoding, the floating-point scalar register f[rs1], v0.t masking, and per-element vd[i] = f[rs1] - vs2[i].

funct6=100111, funct3=101, and opcode=1010111 identify this OP-V FP arithmetic form.

In vfrsub.vf vd, vs2, rs1, vm, vm controls execution masking; vm=0 uses v0.t and vm=1 is unmasked.

For `.vf` forms, rs1 names a floating-point register f[rs1], not an integer GPR value.

Results, NaNs, infinities, rounding, and fflags follow the official vector floating-point rules.

RISC-V Unprivileged ISA Manual: V extension vector floating-point instructions

Vector Execution Context

When reading VFRSUB.VF, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vf: one vector source and one floating-point scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Constant Minus Vector

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfrsub.vf v1, v2, ft0 # v1[i] = ft0 - v2[i]».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

It subtracts the vector element from the scalar; it is not a reduction or an integer reverse subtract.

Only elements within VL whose execution mask is true execute; inactive and tail elements follow the current vma/vta policy.

Ordinary RVV FP arithmetic uses the floating-point rounding environment frm / dynamic rounding semantics, not fixed-point vxrm.

Do not treat finite demo values in the browser animation as a full IEEE 754 exception simulator; NaN, infinity, and fflags follow the official manual.

FAQ

Does VFRSUB.VF use vxrm?

No. Ordinary RVV FP arithmetic uses the floating-point rounding environment frm or the instruction-defined FP rounding rule; vxrm is for fixed-point rounding instructions.

What does the vm operand mean for VFRSUB.VF?

vm=0 uses v0.t as the execution mask; vm=1 is unmasked. It is not an ordinary data source register.