Does VFRSUB.VF use vxrm?
No. Ordinary RVV FP arithmetic uses the floating-point rounding environment frm or the instruction-defined FP rounding rule; vxrm is for fixed-point rounding instructions.
VFRSUB.VF
RISC-V VFRSUB.VF Instruction Details
Instruction ManualOP-VVFRSUB.VF performs vector-scalar FP reverse subtract on active elements within VL: vd[i] = f[rs1] - vs2[i].
Instruction Syntax
vfrsub.vf vd, vs2, rs1, vm
Operand Breakdown
32-bit OP-V encoding: funct6=100111, funct3=101, opcode=1010111. rs1 selects an FP f register, not an integer register. At FLEN>SEW a valid NaN box supplies low SEW bits; otherwise use canonical NaN. FLEN<SEW is reserved.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
Each element computes f[rs1] - vs2[i], rounded using dynamic frm; active-element exceptions accrue in fflags.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
VVector OperationsFloating-Point
Instruction Behavior
Active elements compute vd[i] = f[rs1] - vs2[i]: scalar minus vector, rounded using dynamic frm, with exceptions accrued in fflags. vm=0 uses v0.t; vm=1 is unmasked. vxrm does not control this operation.
VFRSUB.VF Decode And Execute Animation
Decode the OP-V encoding and execute reverse FP subtraction lane by lane: each active lane computes f[rs1] - vs2[i].
Instruction input
vfrsub.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x9c855257
31..26
25
24..20
19..15
14..12
11..7
6..0
100111
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1.5 - 1 -> 0.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1.5 - 1
0.5
i=1active
1.5 - 1.5
0
i=2skip
v0.t=0, not executed
--
i=3active
1.5 - 2.5
-1
i=4active
1.5 - -3
4.5
i=5active
1.5 - 3.5
-2
i=6skip
v0.t=0, not executed
--
i=7active
1.5 - 4.5
-3
SEW=32 / binary32 inputs are represented in the current format before f[rs1] - vs2[i] is rounded under RNE. FLEN=64 is fixed; SEW=32 scalars are assumed validly NaN-boxed. Only finite results are calculated; overflow and full fflags are outside the model. The architectural instruction uses dynamic frm.
Quick Understanding & Search Notes
VFRSUB.VF is best understood through OP-V encoding, the floating-point scalar register f[rs1], v0.t masking, and per-element vd[i] = f[rs1] - vs2[i].
funct6=100111, funct3=101, and opcode=1010111 identify this OP-V FP arithmetic form.
In vfrsub.vf vd, vs2, rs1, vm, vm controls execution masking; vm=0 uses v0.t and vm=1 is unmasked.
For `.vf` forms, rs1 names a floating-point register f[rs1], not an integer GPR value.
Results, NaNs, infinities, rounding, and fflags follow the official vector floating-point rules.
With FLEN>SEW, use the low SEW scalar bits only for a valid NaN box; otherwise use canonical NaN. FLEN<SEW is reserved.
Vector Execution Context
32-bit OP-V encoding: funct6=100111, funct3=101, opcode=1010111. rs1 selects an FP f register, not an integer register. At FLEN>SEW a valid NaN box supplies low SEW bits; otherwise use canonical NaN. FLEN<SEW is reserved.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
Each element computes f[rs1] - vs2[i], rounded using dynamic frm; active-element exceptions accrue in fflags.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
Common Usage Scenarios
Constant Minus Vector
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: ft0=8, v2=[1,2,3,4] → v1=[7,6,5,4]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V encoding: funct6=100111, funct3=101, opcode=1010111. rs1 selects an FP f register, not an integer register. At FLEN>SEW a valid NaN box supplies low SEW bits; otherwise use canonical NaN. FLEN<SEW is reserved.
- Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Semantic Check
- Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
- Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
- Each element computes f[rs1] - vs2[i], rounded using dynamic frm; active-element exceptions accrue in fflags.
- V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
- Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
Pitfalls / Common Confusions
It subtracts the vector element from the scalar; it is not a reduction or an integer reverse subtract.
Only elements within VL whose execution mask is true execute; inactive and tail elements follow the current vma/vta policy.
Ordinary RVV FP arithmetic uses the floating-point rounding environment frm / dynamic rounding semantics, not fixed-point vxrm.
Do not treat finite demo values in the browser animation as a full IEEE 754 exception simulator; NaN, infinity, and fflags follow the official manual.
FAQ
What does the vm operand mean for VFRSUB.VF?
vm=0 uses v0.t as the execution mask; vm=1 is unmasked. It is not an ordinary data source register.