Does VFADD.VF use vxrm?
No. Ordinary RVV FP arithmetic uses the floating-point rounding environment frm or the instruction-defined FP rounding rule; vxrm is for fixed-point rounding instructions.
VFADD.VF
RISC-V VFADD.VF Instruction Details
Instruction ManualV-typeVFADD.VF performs vector-scalar FP add on active elements within VL: vd[i] = vs2[i] + f[rs1].
Instruction Syntax
vfadd.vf vd, vs2, rs1[, v0.t]
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.
rs1 selects FP register f0–f31; with FLEN>SEW, valid NaN-boxing is required or the canonical NaN is supplied. Unsupported FP widths have reserved encodings.
Active elements add vs2[i]+f[rs1] using dynamic frm; only active-element exceptions accrue in fflags. Invalid frm use is reserved even at VL=0; FS=Off raises illegal instruction.
Require V, enabled vector state, and supported vtype. Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); VL=0 leaves the entire destination unchanged. Omitting v0.t means vm=1. Inactive/tail elements follow vma/vta; masked vd cannot overwrite v0, and v0 cannot supply both EEW=1 and SEW sources.
VVector AddFloating-Point
Instruction Behavior
VFADD.VF is an RVV single-width floating-point addition instruction with syntax vfadd.vf vd, vs2, rs1, vm. Each active element uses the current SEW FP format to execute vd[i] = vs2[i] + f[rs1]; the scalar source is the floating-point register f[rs1], not integer x[rs1]. When FLEN is greater than SEW, only the low SEW bits of a valid NaN-boxed scalar are used; otherwise the canonical NaN is used. With vm=0, v0.t controls active elements; with vm=1, execution is unmasked. Rounding mode and exception flags follow the official RVV floating-point rules, and fixed-point vxrm does not control these instructions.
VFADD.VF Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP addition with the second source from scalar f[rs1].
Instruction input
vfadd.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x00855257
31..26
25
24..20
19..15
14..12
11..7
6..0
000000
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 + 1.5 -> 2.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 + 1.5
2.5
i=1active
1.5 + 1.5
3
i=2skip
v0.t=0, not executed
--
i=3active
2.5 + 1.5
4
i=4active
-3 + 1.5
-1.5
i=5active
3.5 + 1.5
5
i=6skip
v0.t=0, not executed
--
i=7active
4.5 + 1.5
6
This finite-add teaching model fixes VLEN=4096, LMUL=m1, vstart=0, and frm=RNE, with VS/FS enabled and the selected SEW supported. The scalar is read at FLEN=64, with valid NaN-boxing assumed for SEW=32. Inputs are represented as binary32, then each active sum rounds under RNE; inactive/tail elements follow ma/ta without a definite displayed value. NaNs, infinities, invalid NaN boxes, overflow, and fflags are outside this model; the real instruction handles these legal FP conditions using dynamic frm and the official exception rules.
Quick Understanding & Search Notes
VFADD.VF is best understood through OP-V encoding, the floating-point scalar register f[rs1], v0.t masking, and per-element vd[i] = vs2[i] + f[rs1].
funct6=000000, funct3=101, and opcode=1010111 identify this OP-V FP arithmetic form.
In vfadd.vf vd, vs2, rs1, vm, vm controls execution masking; vm=0 uses v0.t and vm=1 is unmasked.
For `.vf` forms, rs1 names a floating-point register f[rs1], not an integer GPR value.
When FLEN > SEW, a scalar f[rs1] that is not validly NaN-boxed supplies the canonical NaN; an unsupported vector FP EEW is reserved.
mstatus.FS=Off causes an illegal-instruction exception for vector floating-point instructions.
Results, NaNs, infinities, rounding, and fflags follow the official vector floating-point rules.
All vector FP instructions require a valid dynamic frm; using an invalid frm remains reserved even at VL=0 or with no active elements. Only active-element FP exceptions accrue in fflags.
Vector Execution Context
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.
rs1 selects FP register f0–f31; with FLEN>SEW, valid NaN-boxing is required or the canonical NaN is supplied. Unsupported FP widths have reserved encodings.
Active elements add vs2[i]+f[rs1] using dynamic frm; only active-element exceptions accrue in fflags. Invalid frm use is reserved even at VL=0; FS=Off raises illegal instruction.
Require V, enabled vector state, and supported vtype. Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); VL=0 leaves the entire destination unchanged. Omitting v0.t means vm=1. Inactive/tail elements follow vma/vta; masked vd cannot overwrite v0, and v0 cannot supply both EEW=1 and SEW sources.
Common Usage Scenarios
Scientific Computing
Assume V/vector state enabled, vstart=0, supported e32,m1, VLMAX≥4, and a0=4. The example is unmasked, so all four body elements execute. FP state is enabled, frm=RNE, ft0=1.5 (validly NaN-boxed when FLEN>32), and v2=[1,2,-3,4.5], giving v1=[2.5,3.5,-1.5,6]. Tail elements follow ta without assumed zeroing.
DSP
Assume V/vector state enabled, vstart=0, supported e32,m1, VLMAX≥4, and a0=4. The example is unmasked, so all four body elements execute. FP state is enabled, frm=RNE, ft0=1.5 (validly NaN-boxed when FLEN>32), and v2=[1,2,-3,4.5], giving v1=[2.5,3.5,-1.5,6]. Tail elements follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed and equal sources read equal initial values.
- rs1 selects FP register f0–f31; with FLEN>SEW, valid NaN-boxing is required or the canonical NaN is supplied. Unsupported FP widths have reserved encodings.
Semantic Check
- Active elements add vs2[i]+f[rs1] using dynamic frm; only active-element exceptions accrue in fflags. Invalid frm use is reserved even at VL=0; FS=Off raises illegal instruction.
- Require V, enabled vector state, and supported vtype. Active elements satisfy vstart≤i<vl and (vm=1 or v0[i]=1); VL=0 leaves the entire destination unchanged. Omitting v0.t means vm=1. Inactive/tail elements follow vma/vta; masked vd cannot overwrite v0, and v0 cannot supply both EEW=1 and SEW sources.
Pitfalls / Common Confusions
The scalar source is the floating-point register f[rs1], not integer x[rs1].
Only elements within VL whose execution mask is true execute; inactive and tail elements follow the current vma/vta policy.
Ordinary RVV FP arithmetic uses the floating-point rounding environment frm / dynamic rounding semantics, not fixed-point vxrm.
When FLEN is greater than SEW, f[rs1] must be validly NaN-boxed; otherwise this scalar input is treated as the canonical NaN.
If mstatus.FS is Off, executing a vector floating-point instruction raises an illegal-instruction exception.
Do not treat finite demo values in the browser animation as a full IEEE 754 exception simulator; NaN, infinity, and fflags follow the official manual.
FAQ
What does the vm operand mean for VFADD.VF?
vm=0 uses v0.t as the execution mask; vm=1 is unmasked. It is not an ordinary data source register.
Do inactive VFADD.VF elements set fflags?
No. Only exceptions from active FP elements accrue in fflags. A valid frm is still required with no active elements; mstatus.FS=Off raises an illegal-instruction exception.