Is the estimate result implementation-defined?
No. The V extension defines the 7-bit estimate and special-input handling rules.
VFRSQRT7.V
RISC-V VFRSQRT7.V Instruction Details
Instruction ManualOP-VCompute approximate 1/√x (7-bit accuracy) for each float element of vs2, writing to vd.
Instruction Syntax
vfrsqrt7.v vd, vs2, vm
Operand Breakdown
32-bit OP-V encoding: funct6=010011, funct3=001, opcode=1010111. vs1=00100 is a fixed VFUNARY1 selector, not a second vector source.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
The specified 7-bit lookup and special cases determine the result independently of frm. ±0 returns same-sign infinity with DZ; negative nonzero values or sNaN return canonical NaN with NV; +∞ returns +0; qNaN returns canonical NaN.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
VVector OperationsFloating-Point
Instruction Behavior
Produce a table-defined 7-bit reciprocal square-root estimate. Output is independent of dynamic frm, but valid frm is required. Zeros, infinities, NaNs, and negatives follow the specified special cases.
VFRSQRT7.V Reciprocal square-root estimate animation
Qualitative encoding demo: fixed SEW=32, LMUL=m1, VLEN=4096, vl=1, vstart=0, vm=1, ta, valid frm=RNE, valid vtype, and enabled VS/FS. Shows finite FP32 encoding and negative/±0 special cases; positive-input table values, infinity and NaN inputs are outside the model. Teaching steps are not processor cycles.
Step 1/5
VFUNARY1 OP-V encoding: vs1=00100, funct3=001, vm=1.
v0-v31; vm=1
v0-v31; vm=1
finite FP32 demo value
funct6
010011
vm
1
vs2
01000
vs1
00100
funct3
001
vd
00100
opcode
1010111
hex: 4e821257
See the official source for complete special cases and ordinary-input lookup rules. This demo gives concrete results and newly raised exceptions only for finite negatives and ±0; it does not clear existing fflags.
Quick Understanding & Search Notes
VFRSQRT7.V is a table-defined 7-bit estimate instruction, not ordinary FP divide or square-root.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Special-case results and exception flags should be handled using the official estimate-instruction tables.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
VFUNARY1 vs1=00100 is a fixed selector; funct6=010011, funct3=001, opcode=1010111.
-0 returns -∞ and +0 returns +∞, both raising DZ; negative nonzero values and sNaN return canonical NaN with NV. +∞ returns +0; qNaN returns canonical NaN without an exception.
Positive finite inputs produce normal estimates using the specified table. The output is independent of dynamic frm, but valid frm is still required.
Vector Execution Context
32-bit OP-V encoding: funct6=010011, funct3=001, opcode=1010111. vs1=00100 is a fixed VFUNARY1 selector, not a second vector source.
Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
The specified 7-bit lookup and special cases determine the result independently of frm. ±0 returns same-sign infinity with DZ; negative nonzero values or sNaN return canonical NaN with NV; +∞ returns +0; qNaN returns canonical NaN.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
Common Usage Scenarios
Vector Normalization
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v2=[1,1,1,1] → v1=[0.99609375,0.99609375,0.99609375,0.99609375]. Tails follow ta without assumed zeroing.
Newton-Raphson
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v2=[1,1,1,1] → v1=[0.99609375,0.99609375,0.99609375,0.99609375]. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V encoding: funct6=010011, funct3=001, opcode=1010111. vs1=00100 is a fixed VFUNARY1 selector, not a second vector source.
- Vector operands and results have SEW bits and EMUL=LMUL. Same-width source/destination overlap is legal; equal sources require consistent initial bits. An ordinary masked destination cannot overlap v0.
Semantic Check
- Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
- Prestart elements are unchanged. At vstart≥vl or vl=0 all destination elements, including tails, are unchanged. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeroing.
- The specified 7-bit lookup and special cases determine the result independently of frm. ±0 returns same-sign infinity with DZ; negative nonzero values or sNaN return canonical NaN with NV; +∞ returns +0; qNaN returns canonical NaN.
- V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
- Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
Pitfalls / Common Confusions
Check the official special-case tables for zeros, infinities, NaNs, and negative inputs; do not label the zero-input result implementation-defined.
The estimate has limited precision and usually needs later refinement for high precision.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.