Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFRSQRT7.V
RISC-V VFRSQRT7.V Instruction Details
Instruction ManualOP-VCompute approximate 1/√x (7-bit accuracy) for each float element of vs2, writing to vd.
Instruction Syntax
vfrsqrt7.v vd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsFloating-Point
Instruction Behavior
VFRSQRT7.V produces the 7-bit floating-point estimate defined by the V extension. Special inputs such as zeros, infinities, NaNs, and negatives follow the spec tables; do not describe it as ordinary division/square-root rounded by frm. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
VFRSQRT7.V Reciprocal square-root estimate animation
Shows VFUNARY1 fields, special-value boundaries, and the Table 57 lookup boundary.
Step 1/5
VFUNARY1 OP-V encoding: vs1=00101, funct3=001, vm=1.
v0-v31; v0 disallowed
v0-v31; v0 disallowed
finite FP demo value
funct6
010011
vm
1
vs2
01000
vs1
00101
funct3
001
vd
00100
opcode
1010111
Use the official manual for the complete special-value table and Table 57 values; this animation does not reimplement every table entry.
Quick Understanding & Search Notes
VFRSQRT7.V is a table-defined 7-bit estimate instruction, not ordinary FP divide or square-root.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Special-case results and exception flags should be handled using the official estimate-instruction tables.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
Vector Execution Context
When reading VFRSQRT7.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Normalization
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfrsqrt7.v v1, v2 # v1[i] ≈ 1/√v2[i] (7-bit)».
Newton-Raphson
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfrsqrt7.v v1, v2 # v1[i] ≈ 1/√v2[i] (7-bit)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OP-V.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Check the official special-case tables for zeros, infinities, NaNs, and negative inputs; do not label the zero-input result implementation-defined.
The estimate has limited precision and usually needs later refinement for high precision.
Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions, and the base V extension does not automatically include half-precision arithmetic.
FAQ
Is the estimate result implementation-defined?
No. The V extension defines the 7-bit estimate and special-input handling rules.