Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFREDMIN.VS
RISC-V VFREDMIN.VS Instruction Details
Instruction ManualR-typeOrdered reduction of vs2 active elements to float min, writing to vd[0]; vs1[0] initial.
Instruction Syntax
vfredmin.vs vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector ReductionFloating-Point
Instruction Behavior
VFREDMIN.VS performs vector floating-point reduction, writing the reduction result to vd[0] with vs1[0] as the initial value. Min/max reductions follow the RVV floating-point min/max rules. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.
Quick Understanding & Search Notes
VFREDMIN.VS is a reduction instruction: multiple active elements are combined into a scalar-like result in element 0 of a vector register.
vs1[0] is the initial reduction value; the whole vs1 vector is not a peer input.
The reduction result is in element 0; other elements follow the specified non-result element rules.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Common Usage Scenarios
Vector Reduction
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfredmin.vs v1, v2, v3, vm».
Minimum
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfredmin.vs v1, v2, v3, vm».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vs1[0] supplies initial minimum. Only vd[0] written.
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.