Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFREDOSUM.VS
RISC-V VFREDOSUM.VS Instruction Details
Instruction ManualR-typeOrdered reduction sum of vs2 active float elements to vd[0]; vs1[0] initial.
Instruction Syntax
vfredosum.vs vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector ReductionFloating-Point
Instruction Behavior
VFREDOSUM.VS performs vector floating-point reduction, writing the reduction result to vd[0] with vs1[0] as the initial value. Ordered sum reduces in element order for a defined rounding path. Vector FP32/FP64 operation requires the corresponding scalar F/D support; FP16 is controlled by the relevant vector half-precision extensions; do not assume the base V extension includes half-precision arithmetic.
Quick Understanding & Search Notes
VFREDOSUM.VS is a reduction instruction: multiple active elements are combined into a scalar-like result in element 0 of a vector register.
vs1[0] is the initial reduction value; the whole vs1 vector is not a peer input.
Ordered sum emphasizes a specified reduction order.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Vector Execution Context
When reading VFREDOSUM.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Sum
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmv.s.f v1, ft0 # init with 0.0 vfredosum.vs v1, v2, v1 # v1[0] = sum(v2), vm».
Dot Product
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmv.s.f v1, ft0 # init with 0.0 vfredosum.vs v1, v2, v1 # v1[0] = sum(v2), vm».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Ordered reduction guarantees reproducibility but may be slower — unordered vfredusum.vs allows arbitrary association.
vs1[0] serves as accumulator initial value (typically 0.0).
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.
FAQ
Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.