Is the seed written when no elements are active or vl=0?
With vl>0 and no active elements, copy vs1[0] unchanged to vd[0], without canonicalizing NaNs or raising exception flags. With vl=0, leave the destination unchanged.
VFREDOSUM.VS
RISC-V VFREDOSUM.VS Instruction Details
Instruction ManualOPFVVWhen vl>0, reduce vs1[0] and active vs2 elements using floating-point ordered sum, writing the result to vd[0].
Instruction Syntax
vfredosum.vs vd, vs2, vs1, vm
Operand Breakdown
vs2 is a SEW-wide vector register group; the result is in vd[0], and other destination elements are tails governed by vta. vma does not control the scalar result. The destination may overlap sources and the v0 mask.
vs1[0] is the always-included SEW-wide scalar seed; vd[0] is the result in one vector register, independent of LMUL. Nonzero vstart raises illegal instruction.
Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
vl=0 leaves the destination unchanged. With vl>0 and every element masked off, copy the seed unchanged, without canonicalizing NaNs or raising exception flags.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
VVector ReductionFloating-Point
Instruction Behavior
VFREDOSUM.VS: Add in element order, rounding each addition using dynamic frm. The scalar seed always participates, even if every vector element is masked off; vl=0 leaves the destination unchanged. Other destination elements are tails governed by vta. V includes FP32/FP64 support and depends on F/D; SEW=16 arithmetic requires Zvfh.
VFREDOSUM.VS Reduction animation
Fixed SEW=32, LMUL=m1, VLEN=4096, vstart=0, frm=RNE, valid vtype, and enabled VS/FS. Inputs are represented as FP32; each addition rounds to FP32 under RNE. Nonfinite results and exception flags are outside the model. An empty element list explicitly means vl=0. The destination may overlap sources and v0.
Step 1/5
OP-V encoding: funct6=000011, funct3=001, vm=0.
v0-v31
single-width source
scalar seed in element 0
finite FP32; RNE
finite FP32 values; empty = vl=0
one bit per value
funct6
000011
vm
0
vs2
01000
vs1
01100
funct3
001
vd
00100
opcode
1010111
hex: 0c861257
Writeback
v4[0] = 8
Quick Understanding & Search Notes
When vl>0, reduce vs1[0] and active vs2 elements using floating-point ordered sum, writing the result to vd[0].
OP-V: funct6=000011, funct3=001; vs1 selects the scalar seed held in a vector register.
vm=0 uses v0.t to select active vs2 elements; vm=1 is unmasked. vs1[0] is included regardless of masking.
With vl>0, the result is in vd[0]; all other destination elements follow vta tail policy. vma does not control the scalar result.
vl=0 leaves the destination unchanged; nonzero vstart raises illegal instruction.
Add in element order, rounding each addition using dynamic frm.
V supports FP32/FP64; SEW=16 requires Zvfh. Valid frm is required; vxrm does not control these FP operations.
Vector Execution Context
vs2 is a SEW-wide vector register group; the result is in vd[0], and other destination elements are tails governed by vta. vma does not control the scalar result. The destination may overlap sources and the v0 mask.
vs1[0] is the always-included SEW-wide scalar seed; vd[0] is the result in one vector register, independent of LMUL. Nonzero vstart raises illegal instruction.
Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
vl=0 leaves the destination unchanged. With vl>0 and every element masked off, copy the seed unchanged, without canonicalizing NaNs or raising exception flags.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
Common Usage Scenarios
Vector Sum
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; after vsetvli, vl=4 and vstart=0. Inputs are binary32; f0, when used, is validly NaN-boxed at FLEN=64. The example is unmasked: v3[0]=0, v2=[1,2,3,4] → v1[0]=10. Tails follow ta without assumed zeroing.
Dot Product
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1, VLMAX≥4, and x10=4; after vsetvli, vl=4 and vstart=0. Inputs are binary32; f0, when used, is validly NaN-boxed at FLEN=64. The example is unmasked: v3[0]=0, v2=[1,2,3,4] → v1[0]=10. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vs2 is a SEW-wide vector register group; the result is in vd[0], and other destination elements are tails governed by vta. vma does not control the scalar result. The destination may overlap sources and the v0 mask.
- vs1[0] is the always-included SEW-wide scalar seed; vd[0] is the result in one vector register, independent of LMUL. Nonzero vstart raises illegal instruction.
Semantic Check
- Assembly vm denotes optional v0.t: omission means vm=1; v0.t means vm=0, selecting active vs2 elements. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
- vl=0 leaves the destination unchanged. With vl>0 and every element masked off, copy the seed unchanged, without canonicalizing NaNs or raising exception flags.
- V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and valid frm; invalid frm use is reserved even at vl=0. vxrm does not control these FP operations.
Pitfalls / Common Confusions
The scalar seed is vs1[0]; the result is vd[0]. Other destination elements are tails and are not guaranteed unchanged.
vl=0 does not copy the seed. With vl>0 and no active elements, copy vs1[0] unchanged, without canonicalizing NaNs or raising exception flags.
Nonzero vstart raises illegal instruction; the destination may overlap sources and the v0 mask.
Add in element order, rounding each addition using dynamic frm.