Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VREDSUM.VS
RISC-V VREDSUM.VS Instruction Details
Instruction ManualR-typeVREDSUM.VS uses the vs1[0] seed to perform sum reduction over active vs2 elements, writing only vd[0].
Instruction Syntax
vredsum.vs vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group, with the reduction result written to element 0.
vs2: vector source being reduced.
vs1[0]: reduction seed, not a second element-wise vector source.
VVector Reduction
Instruction Behavior
VREDSUM.VS is a RISC-V V extension single-width integer reduction instruction. Syntax is `vredsum.vs vd, vs2, vs1, vm`; it uses vs1[0] as the seed, includes only masked-in active vs2 elements within the current vl in the sum reduction, and writes the final SEW-width result to vd[0]. Integer overflow wraps at SEW width.
VREDSUM.VS Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VREDSUM uses vs1[0] as the seed, reduces only active vs2 elements, and writes the SEW-width result to vd[0].
Instruction input
vredsum.vs
OP-V encodingvredsum.vs
funct6
000000
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
acc
0x0003
0x0007
0x0007
0x0018
0x001a
0x0021
0x0021
0x0025
v8
0x0004
0x0009
0x0011
0x0002
0x0007
0x0020
0x0004
0x0009
acc+
acc+
acc+
acc+
acc+
acc+
acc+
acc+
v0.t
1
0
1
1
1
0
1
1
v4
...
tail
tail
tail
tail
tail
tail
tail
Current step
Show OP-V 32-bit encoding fields
vredsum.vs uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, vs1[0]-seeded reduction integer sum reduction, mask participation filtering, and vd[0] writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VREDSUM.VS is single-width integer sum reduction. It uses vs1[0] as the scalar seed, accumulates active elements from vs2, and writes the final result to vd[0]; it does not broadcast the result to the whole vector.
This page follows the official RISC-V V extension: vector instructions operate on body elements within the current vl. Unmasked forms operate on all body elements; forms with vm use v0 as the execution mask when vm=0. SEW, LMUL, tail policy, and mask policy come from the current vtype, usually set by vsetvli, vsetivli, or vsetvl.
vs1[0] is the reduction seed; vs1 is not a second element-wise vector source.
Only active elements participate in the reduction; masked-off elements do not contribute.
The reduction result is written to vd[0]. Reduction instructions have specific vstart restrictions; software should not treat them as element-wise operations restartable from an arbitrary element.
Vector Execution Context
When reading VREDSUM.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Global Aggregate
Understand this scenario with real code like «vredsum.vs v1, v2, v3 # reduce active v2 elements with seed v3[0], result in v1[0]».
Normalization
Understand this scenario with real code like «vredsum.vs v1, v2, v3 # reduce active v2 elements with seed v3[0], result in v1[0]».
Condition
Use jal x0, target or j target.
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vs1[0] is the reduction seed; do not treat the whole vs1 register as a second element-wise source.
Only vd[0] holds the reduction result; other destination elements are not per-lane outputs.
vs2 elements masked off by v0.t do not participate, while the vs1[0] seed remains the starting value.
A reduction is not an ordinary element-wise ALU instruction; do not interpret the result as being broadcast to every element.
Do not treat integer reduction as an element-wise operation restartable from an arbitrary vstart; the official requirement is vstart=0.
FAQ
Where does the seed for VREDSUM.VS come from?
The seed comes from element 0 of vs1, namely vs1[0].
Does VREDSUM.VS modify all destination elements?
The effective reduction result is in vd[0]. Other destination elements are not element-wise reduction results and should be understood according to the specification rules for tail/destination elements.