Does VREDOR.VS write the result to every vd element?
No. The effective reduction result is written only to vd[0]; it is neither an element-wise output nor a broadcast result.
VREDOR.VS
RISC-V VREDOR.VS Instruction Details
Instruction ManualOPMVV (OP-V)VREDOR.VS uses the vs1[0] seed to perform bitwise OR reduction over active vs2 elements, writing only vd[0].
Instruction Syntax
vredor.vs vd, vs2, vs1, vm
Operand Breakdown
Syntax: vredor.vs vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=000010.
vs2 is a SEW/LMUL vector group; vs1[0] is the SEW seed and vd[0] the SEW result. Each scalar occupies one vector register regardless of LMUL.
With vl>0 the seed always participates, and only active vs2 elements contribute; all masked off still writes the seed. vl=0 leaves vd unchanged; nonzero vstart raises an illegal-instruction exception. Elements beyond vd[0] are tail governed by vta.
vd may overlap sources or v0. Equal vs2/vs1 must read a consistent element 0 from the same register. v0 cannot provide both the EEW=1 mask and SEW data. Source-group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1, vstart=0 and VLEN=4096; teaching steps are not processor cycles.
VVector Reduction
Instruction Behavior
VREDOR.VS is a RISC-V V extension single-width integer reduction instruction. Syntax is `vredor.vs vd, vs2, vs1, vm`; it uses vs1[0] as the seed, includes only masked-in active vs2 elements within the current vl in the bitwise OR reduction, and writes the final SEW-width result to vd[0]. If vl=0, the destination register is not updated. Each step reduces SEW-bit patterns with the bitwise operation.
VREDOR.VS Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VREDOR uses vs1[0] as the seed, reduces only active vs2 elements, and writes the SEW-width result to vd[0].
Instruction input
vredor.vs
Require V 1.0, enabled vector state and valid supported vtype/SEW. Fix LMUL=m1, vstart=0, VLEN=4096 and VLMAX=4096/16=256. A nonzero vstart for a reduction raises an illegal-instruction exception, so it is not offered as an executable input. A reduction writes element 0 of one vd; the rest is tail governed by vta. vd may overlap sources or v0. With vs2=vs1, the seed must equal vs2[0]. When v0 supplies the EEW=1 mask it cannot also supply SEW data. VL=0 updates no destination elements. Only body is shown without definite inactive/tail values. Steps are teaching stages, not processor cycles.
Execution Context
OP-V encodingvredor.vs
funct6
000010
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
acc
0x0003
0x0013
0x0013
0x001f
0x003f
0x007f
0x007f
0x007f
v8
0x0010
0x0003
0x000c
0x0021
0x0040
0x0005
0x0010
0x0003
acc|
acc|
acc|
acc|
acc|
acc|
acc|
acc|
v0.t
1
0
1
1
1
0
1
1
v4
...
tail
tail
tail
tail
tail
tail
tail
Current step
Show OP-V 32-bit encoding fields
vredor.vs uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows OP-V field decode, active-element reads, integer bitwise OR reduction seeded by vs1[0], mask participation filtering, and vd[0] writeback. These are teaching stages; they do not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VREDOR.VS is a single-width integer reduction instruction; the result is collected in element 0 of the destination vector register.
32-bit OP-V: opcode=1010111 and funct3=010 (OPMVV); all data operands and the result of vredor.vs have SEW bits.
vs2 supplies a vector group; vs1[0] supplies the seed and vd[0] holds the result. Each scalar occupies one vector register regardless of LMUL.
With vl>0, the seed always participates and only active vs2 elements contribute; all masked off still copies the seed to vd[0]. vl=0 updates no destination elements.
Destination elements beyond vd[0] are tail governed by vta. vd may overlap sources or v0; v0 cannot supply both the EEW=1 mask and SEW source data.
Require enabled vector state and valid supported vtype/SEW; nonzero vstart raises an illegal-instruction exception.
Combine SEW-bit patterns using bitwise OR.
Vector Execution Context
Syntax: vredor.vs vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=000010.
vs2 is a SEW/LMUL vector group; vs1[0] is the SEW seed and vd[0] the SEW result. Each scalar occupies one vector register regardless of LMUL.
With vl>0 the seed always participates, and only active vs2 elements contribute; all masked off still writes the seed. vl=0 leaves vd unchanged; nonzero vstart raises an illegal-instruction exception. Elements beyond vd[0] are tail governed by vta.
vd may overlap sources or v0. Equal vs2/vs1 must read a consistent element 0 from the same register. v0 cannot provide both the EEW=1 mask and SEW data. Source-group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1, vstart=0 and VLEN=4096; teaching steps are not processor cycles.
Common Usage Scenarios
Single-width bitwise OR reduction
Assume enabled V/VS, valid m1, supported SEW, VLEN≥128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v4[0]=3, v12=[16,3,12,33] → v8[0]=63. Reduce the seed with active sources; other destination elements are tail governed by vta. vl=0 leaves the destination unchanged.
Seeded masked reduction
Assume enabled V/VS, valid m1, supported SEW, VLEN≥128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v4[0]=3, v12=[16,3,12,33] → v8[0]=63. Reduce the seed with active sources; other destination elements are tail governed by vta. vl=0 leaves the destination unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vredor.vs vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=000010.
- vs2 is a SEW/LMUL vector group; vs1[0] is the SEW seed and vd[0] the SEW result. Each scalar occupies one vector register regardless of LMUL.
Semantic Check
- With vl>0 the seed always participates, and only active vs2 elements contribute; all masked off still writes the seed. vl=0 leaves vd unchanged; nonzero vstart raises an illegal-instruction exception. Elements beyond vd[0] are tail governed by vta.
- vd may overlap sources or v0. Equal vs2/vs1 must read a consistent element 0 from the same register. v0 cannot provide both the EEW=1 mask and SEW data. Source-group starts align to EMUL, EMUL≤8.
- Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1, vstart=0 and VLEN=4096; teaching steps are not processor cycles.
Pitfalls / Common Confusions
vs1[0] is the reduction seed; do not treat the whole vs1 register as a second element-wise source.
Only vd[0] holds the reduction result; other destination elements are not per-lane outputs.
vs2 elements masked off by v0.t do not participate, while the vs1[0] seed remains the starting value.
A reduction is not an ordinary element-wise ALU instruction; do not interpret the result as being broadcast to every element.
Do not treat integer reduction as an element-wise operation restartable from an arbitrary vstart; the official requirement is vstart=0.
FAQ
What is the role of vs1 in VREDOR.VS?
vs1[0] supplies the reduction seed; the whole vs1 vector is not a same-lane second input paired with vs2.
How do all-masked-off and vl=0 differ for VREDOR.VS?
With vl>0 and every vs2 element masked off, the vs1[0] seed is still written to vd[0]. With vl=0, the destination register is not updated.