Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFREDUSUM.VS
RISC-V VFREDUSUM.VS Instruction Details
Instruction ManualOP-VSum vs1[0] and active FP elements of vs2 through an implementation-selected reduction tree into vd[0]; the tree must be deterministic for a given vtype and vl.
Instruction Syntax
vfredusum.vs vd, vs2, vs1, vm
Operand Breakdown
32-bit OP-V encoding: funct6=000001, funct3=001, opcode=1010111. vs1 selects a vector register; .vs reduction reads only element 0, while .vv reads per element.
vs1[0] is always included; active vs2 elements are reduced. The result is vd[0] of one vector register; other elements are tails governed by vta, and vma does not control the scalar result. The destination may overlap sources and v0. Nonzero vstart raises illegal instruction.
Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
vl=0 leaves all destination elements unchanged. At vl>0 with no active vs2 elements, a NaN seed may pass through or be canonicalized, with NV permitted for sNaN; finite seeds follow the reduction rules.
The tree must be deterministic for a given vtype and vl. Nodes may use at least SEW range and precision, rounding with dynamic frm; the root rounds again to SEW. Different implementations need not produce identical numerical results.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
VVector ReductionFloating-Point
Instruction Behavior
Reduce vs1[0] and active FP vs2 elements into vd[0]. Implementations select the tree and intermediate precision; the tree must be deterministic for a given vtype and vl. The root rounds to SEW using dynamic frm.
VFREDUSUM.VS Reduction animation
Fixed SEW=32, LMUL=m1, VLEN=4096, vstart=0, frm=RNE, valid vtype, and enabled VS/FS. Inputs are represented as FP32; each addition rounds to FP32 under RNE. Nonfinite results and exception flags are outside the model. An empty element list explicitly means vl=0. The destination may overlap sources and v0.
Step 1/5
OP-V encoding: funct6=000001, funct3=001, vm=0.
v0-v31
single-width source
scalar seed in element 0
finite FP32; RNE
finite FP32 values; empty = vl=0
one bit per value
funct6
000001
vm
0
vs2
01000
vs1
01100
funct3
001
vd
00100
opcode
1010111
hex: 04861257
Writeback
v4[0] = 8
Quick Understanding & Search Notes
VFREDUSUM.VS is a reduction instruction: multiple active elements are combined into a scalar-like result in element 0 of a vector register.
vs1[0] is always included; masked-off and beyond-vl vs2 elements do not contribute to the effective sum.
Each binary-tree node computes an exact sum, then rounds with dynamic frm to a format with at least the SEW FP range and precision; the root is rounded again to the SEW format.
An extra additive identity is permitted: +0.0 for RDN and -0.0 for other rounding modes.
The tree structure must be deterministic for a given vtype and vl; numerical results can still differ between implementations.
With vl>0 and no active vs2 elements, a NaN seed may pass through unchanged or be canonicalized, with NV permitted for sNaN; vl=0 leaves every destination element unchanged.
Vector Execution Context
32-bit OP-V encoding: funct6=000001, funct3=001, opcode=1010111. vs1 selects a vector register; .vs reduction reads only element 0, while .vv reads per element.
vs1[0] is always included; active vs2 elements are reduced. The result is vd[0] of one vector register; other elements are tails governed by vta, and vma does not control the scalar result. The destination may overlap sources and v0. Nonzero vstart raises illegal instruction.
Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
vl=0 leaves all destination elements unchanged. At vl>0 with no active vs2 elements, a NaN seed may pass through or be canonicalized, with NV permitted for sNaN; finite seeds follow the reduction rules.
The tree must be deterministic for a given vtype and vl. Nodes may use at least SEW range and precision, rounding with dynamic frm; the root rounds again to SEW. Different implementations need not produce identical numerical results.
V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
Common Usage Scenarios
Vector Sum
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v3[0]=0, v2=[1,2,3,4] → v1[0]=10. Tails follow ta without assumed zeroing.
High-Perf Reduction
Assume V/VS/FS enabled, valid vtype, valid frm=RNE, supported e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Inputs are binary32; ft0, when used, is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: v3[0]=0, v2=[1,2,3,4] → v1[0]=10. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- 32-bit OP-V encoding: funct6=000001, funct3=001, opcode=1010111. vs1 selects a vector register; .vs reduction reads only element 0, while .vv reads per element.
- vs1[0] is always included; active vs2 elements are reduced. The result is vd[0] of one vector register; other elements are tails governed by vta, and vma does not control the scalar result. The destination may overlap sources and v0. Nonzero vstart raises illegal instruction.
Semantic Check
- Optional assembly vm is written v0.t for vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. One source register cannot be read as both an EEW=1 mask and SEW-wide data.
- vl=0 leaves all destination elements unchanged. At vl>0 with no active vs2 elements, a NaN seed may pass through or be canonicalized, with NV permitted for sNaN; finite seeds follow the reduction rules.
- The tree must be deterministic for a given vtype and vl. Nodes may use at least SEW range and precision, rounding with dynamic frm; the root rounds again to SEW. Different implementations need not produce identical numerical results.
- V 1.0 applies to RV32/RV64, includes FP32/FP64, and depends on F/D; SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. All these vector FP instructions require valid frm, even if independent of it or at vl=0. vxrm does not control them.
- Animation steps are educational, not processor cycles. Fixed VLEN=4096, LMUL=m1, vstart=0, valid vtype, and enabled VS/FS apply; input formats, fixed rounding, and model limits are stated in the animation. VF scalars use FLEN=64, assuming valid NaN-boxing at SEW=32.
Pitfalls / Common Confusions
Implementations may choose different trees and intermediate precision, but the tree must be deterministic for a given vtype and vl; it is not arbitrarily reordered each run.
vfredosum.vs adds in element order and is also a legal implementation of vfredusum.vs.
vl=0 leaves the destination unchanged; at vl>0 destination elements other than vd[0] are tails governed by vta, and vma does not control the reduction scalar.