VFWREDUSUM.VS

RISC-V VFWREDUSUM.VS Instruction Details

Instruction ManualOPFVV

Promote active SEW-wide vs2 floating-point elements to 2*SEW and reduce them with wide vs1[0] in an unordered sum; only wide vd[0] holds the reduction result, and other destination elements are tail.

Instruction Syntax

vfwredusum.vs vd, vs2, vs1, vm

Operand Breakdown

vd[0]: element 0 of a single destination vector register, receiving the 2*SEW reduction result; other destination elements are tail.

vs2: the SEW-wide source vector register group being reduced; active elements are promoted to 2*SEW.

vs1[0]: element 0 of a single vector register, supplying the 2*SEW reduction seed, not a second element-wise vector source.

vm: vm=0 uses v0 to select participating vs2 elements and vm=1 is unmasked; vstart must be 0.

VVector ReductionFloating-Point

Related Search Terms

VFWREDUSUM.VS instruction RISC-V VFWREDUSUM.VS vfwredusum.vs syntax vfwredusum.vs RVV RVV widening FP reduction unordered floating-point sum floating-point reduction tree

Instruction Behavior

VFWREDUSUM.VS is the RVV widening unordered floating-point reduction sum. It promotes active narrow vs2 elements within vl to 2*SEW and combines them with wide vs1[0] in an ISA-permitted deterministic reduction tree; only wide vd[0] holds the reduction result, while other destination elements are tail managed by the current tail policy. With vl=0, no operation is performed and the destination is not updated. The ISA does not prescribe one tree, one intermediate precision at every node, or one numeric result; use VFWREDOSUM.VS when increasing element-order semantics are required.

VFWREDUSUM.VS Decode And Execute Animation

A checkable FP32-to-FP64 reduction example; NaN, infinity, and exception flags are not simulated.

Instruction input

wide scalar result: element 0 of any v0-v31

vs2

SEW narrow source; cannot share a register with wide vs1

vs1

wide seed: element 0 of any register; not v0 when masked

Execution Context

SEW

32 (FP32)

reduction EEW

64 (FP64)

frm

RNE demo

LMUL

VLEN

4096

vstart

vs1[0] seed

finite FP64 demo value

vs2 elements

exactly 4 values representable as finite FP32

v0 mask bits

exactly 4 0/1 bits

active lanes

Encoding Fields

0xc4861257

funct6

110001

vs2

01000

vs1

01100

funct3

001

00100

opcode

1010111

Data Path And Result

Active promoted elements: 1, 3, 4

Reduction trace:

1 + 1 = 2
3 + 4 = 7
2 + 7 = 9

Writeback

v4[0] = 9

This is one legal example tree, not an ISA-mandated unique reduction result.

Step 1/5

Show the OP-V instruction encoding; invalid inputs produce no encoding.

Quick Understanding & Search Notes

VFWREDUSUM.VS combines promoted active vs2 elements with wide vs1[0] in a legal unordered reduction tree; the reduction result is in wide vd[0], other destination elements are tail, and the tree is not uniquely prescribed by the ISA.

vs2 holds SEW-width floating-point inputs; vs1[0], vd[0], and the reduction use 2*SEW width, and vs1/vd are element 0 of single vector registers.

Only active selected source elements within vl are reduced; destination elements other than vd[0] are tail and follow the tail policy.

Floating-point rounding and exception flags follow RVV FP rules; fixed-point vxrm does not control this instruction.

vm=0 uses v0 as the execution mask and vm=1 is unmasked; masked-off source elements are excluded, destination elements other than vd[0] are tail and follow the tail policy, and nonzero vstart is illegal.

RISC-V Unprivileged ISA Manual, Section 31.14.4: Vector Widening Floating-Point Reduction Instructions

Vector Execution Context

When reading VFWREDUSUM.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Widening Sum

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwredusum.vs v4, v8, v12, v0.t # only vd[0] receives a 2*SEW reduction result».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is OPFVV.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Unordered reduction permits different deterministic reduction trees; do not present the page example tree or numeric result as the ISA's unique result.

vs2 is SEW wide, while vs1[0], vd[0], and the reduction result are 2*SEW wide; only vd[0] receives the result.

Use VFWREDOSUM.VS when active elements must be added in increasing order rather than relying on a superficially similar unordered result.

FAQ

Is the VFWREDUSUM.VS result reproducible?

The ISA permits unordered reduction trees; floating-point rounding can vary with implementation or configuration. Use VFWREDOSUM.VS for ordered semantics.

How does VFWREDUSUM.VS handle masking?

With vm=0, v0 selects active source elements; with vm=1, all body source elements participate. Masked-off source elements are excluded, while destination elements other than vd[0] are tail and follow the tail policy.