Promote active SEW-wide vs2 floating-point elements to 2*SEW and reduce them with wide vs1[0] in an unordered sum; only wide vd[0] holds the reduction result, and other destination elements are tail.
Extension condition: V 1.0 on RV32/RV64, with supported FP formats, valid vtype, and enabled VS/FS. Standard V supports SEW=32 to FP64, not a guaranteed SEW=64-to-FP128 path.
VFWREDUSUM.VS is the RVV widening unordered floating-point reduction sum. It promotes active narrow vs2 elements within vl to 2*SEW and combines them with wide vs1[0] in an ISA-permitted deterministic reduction tree; only wide vd[0] holds the reduction result, while other destination elements are tail managed by the current tail policy. With vl=0, no operation is performed and the destination is not updated. The ISA does not prescribe one tree, one intermediate precision at every node, or one numeric result; use VFWREDOSUM.VS when increasing element-order semantics are required.
A checkable FP32-to-FP64 reduction example; with valid vtype, enabled VS/FS, valid frm=RNE, and ta. Inputs are first represented as FP32, the seed as FP64, and every addition rounds to FP64 under RNE. Nonfinite inputs/results and exception flags are outside the model; teaching steps are not processor cycles.
wide scalar result: element 0 of any v0-v31
SEW narrow source; cannot share a register with wide vs1
wide seed: element 0 of any register; not v0 when masked
nonempty finite FP64 demo value
exactly 4 values representable as finite FP32
exactly 4 0/1 bits
0xc4861257Active promoted elements: 1, 3, 4
Reduction trace:
Writeback
v4[0] = 9
This is one legal example tree, not an ISA-mandated unique reduction result.
Show the OP-V instruction encoding; invalid inputs produce no encoding.
VFWREDUSUM.VS combines promoted active vs2 elements with wide vs1[0] in a legal unordered reduction tree; the reduction result is in wide vd[0], other destination elements are tail, and the tree is not uniquely prescribed by the ISA.
Syntax: vfwredusum.vs vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=110001.
vs2 uses EEW=SEW, EMUL=LMUL; the 2×SEW seed vs1[0] and result vd[0] each occupy element 0 of any single vector register (EMUL=1), without even-register alignment. The destination may overlap sources and v0; a register cannot be read with different source EEWs.
Reduce wide vs1[0] and promoted active sources through a tree. Each node has at least the range/precision of the 2×SEW format and rounds under dynamic frm; the final result rounds to 2×SEW. The tree is deterministic for given vtype/vl, but results may differ across implementations. An extra additive identity is permitted (+0 for RDN, -0 otherwise). With no active sources, NaNs may propagate or canonicalize, and sNaN may raise NV.
Omit v0.t for vm=1; include it for vm=0. Masked-off sources raise no FP exceptions; active exceptions accrue in fflags. One register cannot be read as both an EEW=1 mask and different-EEW data source. The seed always participates, independent of mask bit 0. Nonzero vstart is illegal. vl=0 updates no destination and does not copy the seed; other destination elements are tail governed only by vta. ta/ma does not guarantee zeros; successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. This finite model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and RNE; NaNs, infinities, and fflags are not fully simulated.
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. v0.t selects lanes 0, 2, 3; the seed always participates. v12[0](binary64)=1, v8(binary32)=[1,2,3,4], v0 mask=1011 → v4[0](binary64)=9. These additions are exact; the example tree gives this value without implying a unique result for unordered sums in general. Tails follow ta without guaranteed zeros.
The tree must be deterministic for given vtype and vl. Implementations may choose different trees and intermediate precision, so results need not match across implementations. Use VFWREDOSUM.VS for ordered semantics.
With vm=0, v0 selects active source elements; with vm=1, all body source elements participate. Masked-off source elements are excluded, while destination elements other than vd[0] are tail and follow the tail policy.