VFWREDUSUM.VS

RISC-V VFWREDUSUM.VS Instruction Details

Instruction ManualR-type

Widen active vs2 floating-point elements for an unordered reduction sum, using wide vs1[0] as the initial value and writing vd[0].

Instruction Syntax

vfwredusum.vs vd, vs2, vs1, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VZvfhVector ReductionFloating-Point

Related Search Terms

VFWREDUSUM.VS instruction RISC-V VFWREDUSUM.VS vfwredusum.vs syntax vfwredusum.vs RVV widening FP reduction RVV floating point

Instruction Behavior

VFWREDUSUM.VS is the RISC-V V widening floating-point unordered reduction-sum instruction. It widens active narrow vs2 elements to 2*SEW precision and reduces them with the wide initial value vs1[0]; only vd[0] receives the result. Because the reduction is unordered, implementations may choose the reduction tree, so the rounded floating-point result need not match ordered element-by-element reduction.

Quick Understanding & Search Notes

VFWREDUSUM.VS performs a widening floating-point unordered sum; use VFWREDOSUM.VS when fixed element-order semantics are required.

vs2 holds SEW-width floating-point inputs; the reduction and vd[0]/vs1[0] use 2*SEW width.

Only active selected elements within vl are reduced; destination elements beyond the reduction result do not carry results.

Floating-point rounding and exception flags follow RVV FP rules; fixed-point vxrm does not control this instruction.

vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFWREDUSUM.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Widening Sum

Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vfwredusum.vs v2, v4, v3».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Unordered reduction lets implementations choose the reduction tree; the floating-point result need not match ordered element-by-element summation. Use vfwredosum.vs for ordered semantics.

Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.

FAQ

Is the VFWREDUSUM.VS result reproducible?

The ISA permits unordered reduction trees; floating-point rounding can vary with implementation or configuration. Use VFWREDOSUM.VS for ordered semantics.

How does VFWREDUSUM.VS handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.