Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.
VFWREDOSUM.VS
RISC-V VFWREDOSUM.VS Instruction Details
Instruction ManualOPFVVPromote active SEW-wide vs2 elements to 2*SEW and sum them in increasing element order; wide vs1[0] is the seed, only wide vd[0] holds the reduction result, and other destination elements are tail.
Instruction Syntax
vfwredosum.vs vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vfwredosum.vs vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=110011.
vs2 uses EEW=SEW, EMUL=LMUL; the 2×SEW seed vs1[0] and result vd[0] each occupy element 0 of any single vector register (EMUL=1), without even-register alignment. The destination may overlap sources and v0; a register cannot be read with different source EEWs.
Starting from wide vs1[0], promote active vs2 elements and add in increasing index order, rounding every addition to the wide format under dynamic frm. With vl>0 and no active source elements, copy the original seed without NaN canonicalization or new exceptions.
Omit v0.t for vm=1; include it for vm=0. Masked-off sources raise no FP exceptions; active exceptions accrue in fflags. One register cannot be read as both an EEW=1 mask and different-EEW data source. The seed always participates, independent of mask bit 0. Nonzero vstart is illegal. vl=0 updates no destination and does not copy the seed; other destination elements are tail governed only by vta. ta/ma does not guarantee zeros; successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. This finite model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and RNE; NaNs, infinities, and fflags are not fully simulated.
VVector ReductionFloating-Point
Extension condition: V 1.0 on RV32/RV64, with supported FP formats, valid vtype, and enabled VS/FS. Standard V supports SEW=32 to FP64, not a guaranteed SEW=64-to-FP128 path.
Instruction Behavior
VFWREDOSUM.VS is the RVV widening ordered floating-point reduction sum. It promotes active vs2 floating-point elements within vl from SEW to 2*SEW and adds them in increasing element order starting from wide vs1[0]; only wide vd[0] holds the reduction result, while other destination elements are tail managed by the current tail policy. Masked-off elements affect neither the result nor FP exception flags. With vl=0, no operation is performed and the destination is not updated; with nonzero vl but no active source elements, no addition is performed and the seed is written to vd[0].
VFWREDOSUM.VS Decode And Execute Animation
A checkable FP32-to-FP64 reduction example; with valid vtype, enabled VS/FS, valid frm=RNE, and ta. Inputs are first represented as FP32, the seed as FP64, and every addition rounds to FP64 under RNE. Nonfinite inputs/results and exception flags are outside the model; teaching steps are not processor cycles.
Instruction input
wide scalar result: element 0 of any v0-v31
SEW narrow source; cannot share a register with wide vs1
wide seed: element 0 of any register; not v0 when masked
Execution Context
SEW
32 (FP32)
reduction EEW
64 (FP64)
frm
RNE demo
LMUL
m1
VLEN
4096
vstart
0
nonempty finite FP64 demo value
exactly 4 values representable as finite FP32
exactly 4 0/1 bits
active lanes
3
Encoding Fields
0xcc861257funct6
110011
vm
0
vs2
01000
vs1
01100
funct3
001
vd
00100
opcode
1010111
Data Path And Result
Active promoted elements: 1, 3, 4
Reduction trace:
- 1 + 1 = 2
- 2 + 3 = 5
- 5 + 4 = 9
Writeback
v4[0] = 9
This demo follows increasing active-element order.
Step 1/5
Show the OP-V instruction encoding; invalid inputs produce no encoding.
Quick Understanding & Search Notes
VFWREDOSUM.VS promotes narrow vs2 elements and sums them in active-element order starting from wide vs1[0]; the reduction result is in wide vd[0], while other destination elements are tail.
vs2 is a SEW-wide vector group; vs1[0]/vd[0] are 2*SEW-wide scalars in single registers (EMUL=1). Any register is allowed without even-register alignment. The destination may overlap sources and v0.
One register cannot be read with different source EEWs, including mask EEW=1. The wide seed and narrow source cannot share a register; with v0.t neither data source can be v0.
32-bit OP-V: opcode=1010111, funct3=001, funct6=110011. Syntax: vd, vs2, vs1[, v0.t].
Only active vs2 elements participate; the wide seed always participates. Other destination elements are tail, governed only by vta. vl=0 updates no destination and does not copy the seed; nonzero vstart is illegal.
Each wide addition uses dynamic frm; active exceptions accrue in fflags. Invalid frm use is reserved even at vl=0; vxrm is not used.
Ordered sums add in increasing active-element order. With vl>0 and no active sources, copy the original seed without NaN canonicalization or new exceptions.
Vector Execution Context
Syntax: vfwredosum.vs vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=110011.
vs2 uses EEW=SEW, EMUL=LMUL; the 2×SEW seed vs1[0] and result vd[0] each occupy element 0 of any single vector register (EMUL=1), without even-register alignment. The destination may overlap sources and v0; a register cannot be read with different source EEWs.
Starting from wide vs1[0], promote active vs2 elements and add in increasing index order, rounding every addition to the wide format under dynamic frm. With vl>0 and no active source elements, copy the original seed without NaN canonicalization or new exceptions.
Omit v0.t for vm=1; include it for vm=0. Masked-off sources raise no FP exceptions; active exceptions accrue in fflags. One register cannot be read as both an EEW=1 mask and different-EEW data source. The seed always participates, independent of mask bit 0. Nonzero vstart is illegal. vl=0 updates no destination and does not copy the seed; other destination elements are tail governed only by vta. ta/ma does not guarantee zeros; successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. This finite model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and RNE; NaNs, infinities, and fflags are not fully simulated.
Common Usage Scenarios
Widening Ordered FP Sum
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. v0.t selects lanes 0, 2, 3; the seed always participates. v12[0](binary64)=1, v8(binary32)=[1,2,3,4], v0 mask=1011 → v4[0](binary64)=9. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwredosum.vs vd, vs2, vs1[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=110011.
- vs2 uses EEW=SEW, EMUL=LMUL; the 2×SEW seed vs1[0] and result vd[0] each occupy element 0 of any single vector register (EMUL=1), without even-register alignment. The destination may overlap sources and v0; a register cannot be read with different source EEWs.
Semantic Check
- Starting from wide vs1[0], promote active vs2 elements and add in increasing index order, rounding every addition to the wide format under dynamic frm. With vl>0 and no active source elements, copy the original seed without NaN canonicalization or new exceptions.
- Omit v0.t for vm=1; include it for vm=0. Masked-off sources raise no FP exceptions; active exceptions accrue in fflags. One register cannot be read as both an EEW=1 mask and different-EEW data source. The seed always participates, independent of mask bit 0. Nonzero vstart is illegal. vl=0 updates no destination and does not copy the seed; other destination elements are tail governed only by vta. ta/ma does not guarantee zeros; successful execution resets vstart=0.
- V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. This finite model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and RNE; NaNs, infinities, and fflags are not fully simulated.
Pitfalls / Common Confusions
The ordered form adds vs1[0], then active vs2[0] through vs2[vl-1]; do not present it as an implementation-reordered tree.
vs2 is SEW wide, while vs1[0], vd[0], and each accumulation are 2*SEW wide; only vd[0] carries the reduction result.
With vm=0, masked-off elements neither participate in the sum nor set FP exception flags.