Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFWREDOSUM.VS
RISC-V VFWREDOSUM.VS Instruction Details
Instruction ManualOPFVVPromote active SEW-wide vs2 elements to 2*SEW and sum them in increasing element order; wide vs1[0] is the seed, only wide vd[0] holds the reduction result, and other destination elements are tail.
Instruction Syntax
vfwredosum.vs vd, vs2, vs1, vm
Operand Breakdown
vd[0]: element 0 of a single destination vector register, receiving the 2*SEW reduction result; other destination elements are tail.
vs2: the SEW-wide source vector register group being reduced; active elements are promoted to 2*SEW.
vs1[0]: element 0 of a single vector register, supplying the 2*SEW reduction seed, not a second element-wise vector source.
vm: vm=0 uses v0 to select participating vs2 elements and vm=1 is unmasked; vstart must be 0.
VVector ReductionFloating-Point
Instruction Behavior
VFWREDOSUM.VS is the RVV widening ordered floating-point reduction sum. It promotes active vs2 floating-point elements within vl from SEW to 2*SEW and adds them in increasing element order starting from wide vs1[0]; only wide vd[0] holds the reduction result, while other destination elements are tail managed by the current tail policy. Masked-off elements affect neither the result nor FP exception flags. With vl=0, no operation is performed and the destination is not updated; with nonzero vl but no active source elements, no addition is performed and the seed is written to vd[0].
VFWREDOSUM.VS Decode And Execute Animation
A checkable FP32-to-FP64 reduction example; NaN, infinity, and exception flags are not simulated.
Instruction input
wide scalar result: element 0 of any v0-v31
SEW narrow source; cannot share a register with wide vs1
wide seed: element 0 of any register; not v0 when masked
Execution Context
SEW
32 (FP32)
reduction EEW
64 (FP64)
frm
RNE demo
LMUL
m1
VLEN
4096
vstart
0
finite FP64 demo value
exactly 4 values representable as finite FP32
exactly 4 0/1 bits
active lanes
3
Encoding Fields
0xcc861257funct6
110011
vm
0
vs2
01000
vs1
01100
funct3
001
vd
00100
opcode
1010111
Data Path And Result
Active promoted elements: 1, 3, 4
Reduction trace:
- 1 + 1 = 2
- 2 + 3 = 5
- 5 + 4 = 9
Writeback
v4[0] = 9
This demo follows increasing active-element order.
Step 1/5
Show the OP-V instruction encoding; invalid inputs produce no encoding.
Quick Understanding & Search Notes
VFWREDOSUM.VS promotes narrow vs2 elements and sums them in active-element order starting from wide vs1[0]; the reduction result is in wide vd[0], while other destination elements are tail.
vs1[0] is the initial reduction value; the whole vs1 vector is not a peer input.
Ordered sum emphasizes a specified reduction order.
Masked-off or out-of-vl source elements are excluded; destination elements other than vd[0] are tail and follow only the current tail policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
With vl=0, the destination register is not updated; a nonzero vstart raises an illegal-instruction exception for reductions.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Vector Execution Context
When reading VFWREDOSUM.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
High-Precision Sum
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwredosum.vs v4, v8, v12, v0.t # vd[0] = (((vs1[0] + vs2[0]) + ...) + vs2[vl-1])».
Dot Product
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfwredosum.vs v4, v8, v12, v0.t # vd[0] = (((vs1[0] + vs2[0]) + ...) + vs2[vl-1])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPFVV.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The ordered form adds vs1[0], then active vs2[0] through vs2[vl-1]; do not present it as an implementation-reordered tree.
vs2 is SEW wide, while vs1[0], vd[0], and each accumulation are 2*SEW wide; only vd[0] carries the reduction result.
With vm=0, masked-off elements neither participate in the sum nor set FP exception flags.
FAQ
Do these floating-point instructions use vxrm?
No. Ordinary RVV floating-point operations and FP conversions use floating-point frm or an instruction-specified fixed rounding mode; vxrm is for fixed-point rounding instructions.