Do these vector BF16 instructions support any SEW?
No. The official vector BF16 instructions reserve encodings when SEW is not 16; this page animation fixes SEW=16.
VFWMACCBF16.VF
RISC-V VFWMACCBF16.VF Instruction Details
Instruction ManualOP-VBF16 vector-scalar widening fused multiply-accumulate into FP32 vd.
Instruction Syntax
vfwmaccbf16.vf vd, rs1, vs2, vm
Operand Breakdown
vd is both the FP32 accumulator input and result, EEW=32 and EMUL=2*LMUL; BF16 vector sources have EEW=16 and EMUL=LMUL. Groups align to EMUL; the accumulator cannot share a register read with a BF16 source at a different EEW.
rs1 selects a BF16 scalar in f0–f31; require valid NaN-boxing or consume canonical QNaN.
SEW must be 16. vm denotes optional v0.t; omission is unmasked. Only mask-enabled vstart<=i<vl elements execute; vstart>=vl (including vl=0) updates no destination elements.
ZvfbfwmaVector Operations
Instruction Behavior
VFWMACCBF16.VF, with SEW=16, reads a scalar BF16 value from f[rs1], BF16 elements from vs2, and the FP32 accumulator in vd, multiplies the BF16 sources, adds the unrounded product to the corresponding FP32 accumulator, then rounds by frm and writes FP32 vd; it belongs to Zvfbfwma.
VFWMACCBF16.VF Decode And Execute Animation
Decode the OP-V encoding and execute BF16 widening fused multiply-accumulate: each active lane multiplies f[rs1] and vs2[i] as BF16 sources and accumulates into FP32 vd[i].
Instruction input
vfwmaccbf16.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
acc EEWvd accumulator is FP32
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xec855257
31..26
25
24..20
19..15
14..12
11..7
6..0
111011
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma_rne(1.5, 1.5, 0.5) -> 2.75 / 0x40300000
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma_rne(1.5, 1.5, 0.5)
2.75 / 0x40300000
i=1active
fma_rne(-2.25, 1.5, -1)
-4.375 / 0xc08c0000
i=2skip
v0.t=0, not executed
--
i=3active
fma_rne(-6, 1.5, -2.5)
-11.5 / 0xc1380000
i=4active
fma_rne(8, 1.5, 4)
16 / 0x41800000
i=5active
fma_rne(-10, 1.5, -4.5)
-19.5 / 0xc19c0000
i=6skip
v0.t=0, not executed
--
i=7active
fma_rne(-20, 1.5, -8.5)
-38.5 / 0xc21a0000
The teaching context fixes SEW=16, LMUL=m1, VLEN=4096, VLMAX=256, vstart=0, valid vtype, enabled VS/FS, and ta/ma. BF16 sources occupy single registers; the FP32 accumulator occupies an even vd..vd+1 group. Since the accumulator is also a source, it cannot overlap a BF16 source read at a different EEW. Equal BF16 sources require equal bits. Numeric input is represented as FP32 and then as BF16 under RNE; raw patterns directly provide BF16 bits. The exact product-plus-FP32-addend is rounded once by the selected frm; scalar input assumes valid NaN-boxing. VL=0 updates no destination elements; inactive/tail values are unspecified by this display. NaNs, infinities, and fflags are outside this finite-sample model; exceeding its range does not mean an illegal instruction.
SEW=16, BF16 sources come from vs2 and vs1/rs1, and vd is both the FP32 accumulator input and FP32 result. The animation exactly widens BF16 sources first, then shows the equivalent FP32 fused multiply-accumulate path; exception flags follow the official BF16 rules.Quick Understanding & Search Notes
This is the BF16 vector-scalar widening FMA: the syntax is vd, rs1, vs2, vm; rs1 is a BF16 scalar in an FP register, and vd is the FP32 accumulator and result.
OP-V encoding: funct6=111011, funct3=101 (OPFVF), opcode=1010111; the rs1 field selects the BF16 scalar source in an FP register.
Official reserved encoding: any SEW value other than 16 is reserved.
rs1/vs2 sources have EEW=16 BF16, while vd input and output have EEW=32 FP32.
The official equivalent sequence widens the BF16 scalar and vector source to FP32 and then performs vfmacc.vf.
Only active elements within vl execute; with vm=0, v0.t controls activity.
FP32 vd is also a read accumulator source; it cannot overlap a BF16 source that reads the same vector register at a different EEW.
Vector Execution Context
SEW=16. Active elements satisfy vstart<=i<vl and mask enablement. vstart>=vl (including vl=0) updates no destination elements; prestart stays unchanged, while inactive/tail follow vma/vta. BF16 sources use EMUL=LMUL and FP32 accumulator/results use EMUL=2*LMUL<=8. Require valid supported vtype, required extensions and enabled vector/FP state; each active element uses one fused rounding by frm.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, §25.5.5Common Usage Scenarios
Vector Operations
Understand this scenario with real code like «vfwmaccbf16.vf v4, f0, v8 # v4[fp32] += bf16(f0) * bf16(v8[i])».
Machine Learning
Understand this scenario with real code like «vfwmaccbf16.vf v4, f0, v8 # v4[fp32] += bf16(f0) * bf16(v8[i])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OP-V.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
SEW must be 16; other SEW encodings are reserved.
rs1 names a scalar BF16 source in a floating-point register, not an integer-register source.
vs2 is the BF16 vector source, while vd is both the FP32 accumulator input and FP32 output.
Zvfbfwma depends on Zvfbfmin and Zfbfmin.
Do not model this as separate BF16 multiply then BF16 add; the official semantics are widening fused multiply-accumulate.
A scalar BF16 value must be correctly NaN-boxed; otherwise it is consumed as a canonical QNaN. The animation assumes valid NaN-boxing.
FAQ
Is BF16 the same as IEEE binary16?
No. BF16 has 1 sign bit, 8 exponent bits, and 7 fraction bits; it differs from half-precision binary16 in exponent and fraction widths.
Is VFWMACCBF16 the same as ordinary vfmacc?
Not exactly. The official description gives an equivalent sequence that widens BF16 sources to FP32 and then uses vfmacc, but the source format, SEW=16 restriction, and Zvfbfwma requirement are different.