Does VMFEQ.VF write ordinary vector elements?
Each active lane writes one Boolean bit to mask destination vd, not an ordinary vector element.
VMFEQ.VF
RISC-V VMFEQ.VF Instruction Details
Instruction ManualOPFVFPerform lane-wise FP equality comparison and write Boolean results to mask destination vd.
Instruction Syntax
vmfeq.vf vd, vs2, rs1, vm
Operand Breakdown
vd is a single mask destination, one bit per element; rs1 selects an f register, not an integer register. Active elements write vs2[i]==f[rs1]; +0 equals -0, NaNs produce 0, and only active sNaN inputs raise NV.
32-bit OP-V: opcode=1010111, funct6=011000, funct3=101. Omit v0.t for vm=1 or include it for vm=0.
The mask destination may overlap v0. Reading the same register as mask and data with different EEWs is reserved. With LMUL=m1, vd may start at vs2.
Require valid vtype, enabled VS/FS, supported FP formats, and valid frm. With FLEN>SEW an invalid NaN box supplies canonical NaN; FLEN<SEW is reserved. Equality does not round by frm, but invalid frm use remains reserved.
Body is vstart≤i<vl; prestart is unchanged, inactive bits follow vma and mask tails are always agnostic. VL=0 or vstart≥vl updates no destination, including tails. The animation fixes LMUL=m1, VLEN=4096, vstart=0; steps are not processor cycles.
VVector FPCompare
Instruction Behavior
VMFEQ.VF is a RISC-V V-extension vector floating-point compare instruction. For active elements within vl, it evaluates vs2[i] == scalar FP register f[rs1] and writes each Boolean result to the corresponding bit of mask destination vd. vm=0 uses v0.t as the execution mask and vm=1 is unmasked; NaN handling, invalid exception flags, and tail-agnostic result rules follow the official RVV FP compare semantics.
VMFEQ.VF Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP compare: each active lane evaluates vs2[i] == f[rs1] and writes the Boolean result to the destination mask bit.
Instruction input
vmfeq.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmnot rounded by frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x60855257
31..26
25
24..20
19..15
14..12
11..7
6..0
011000
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 == 1.5 -> mask=0
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
This execution does not raise NVLong vectors scroll inside this module without page overflow.
i=0active
1 == 1.5
mask=0
i=1active
1.5 == 1.5
mask=1
i=2skip
v0.t=0, not executed
--
i=3active
2.5 == 1.5
mask=0
i=4active
-3 == 1.5
mask=0
i=5active
3.5 == 1.5
mask=0
i=6skip
v0.t=0, not executed
--
i=7active
4.5 == 1.5
mask=0
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, valid vtype, enabled VS/FS, FLEN=64, and valid frm. The selected binary32/64 is supported; SEW=32 scalars assume valid NaN-boxing. vd is a single mask register and may overlap v0 or start at vs2; masked vs2 cannot be v0 (different EEWs). Different-EEW overlap of vd with vs2 also forces mask-agnostic, regardless of vma. Inactive bits have no definite displayed value; mask tails are always agnostic. VL=0 updates no destination bits. The NV indicator shows what this execution raises without clearing old fflags. Rounding selection does not affect equality, but invalid frm use remains reserved. Steps are not processor cycles.
SEW=32 / binary32 demo accepts finite values or full IEEE hexadecimal bit patterns, so qNaN/sNaN can be checked. Active lanes write 0/1 destination mask bits and show this execution's fflags.NV when required. Officially, VMFEQ/VMFNE raise invalid only for signaling NaN inputs; VMFLT/VMFLE/VMFGT/VMFGE raise invalid for signaling or quiet NaN inputs; VMFNE writes 1 when either operand is NaN, while the other compares write 0.Quick Understanding & Search Notes
VMFEQ.VF compares active vs2[i] with scalar f[rs1] for equality, writing one Boolean bit to mask destination vd.
OP-V: funct6=011000, funct3=101 (OPFVF).
vm=0 uses v0.t as the execution mask; vm=1 is unmasked.
The result is a mask; tails are tail-agnostic.
VMFEQ raises invalid only for signaling NaN inputs.
VMFEQ writes 0 for NaN comparisons.
Require supported formats, valid vtype/frm and enabled VS/FS. Invalid FLEN>SEW NaN-boxes supply canonical NaN; FLEN<SEW is reserved. Inactive elements raise no flags.
Vector Execution Context
vd is a single mask destination, one bit per element; rs1 selects an f register, not an integer register. Active elements write vs2[i]==f[rs1]; +0 equals -0, NaNs produce 0, and only active sNaN inputs raise NV.
32-bit OP-V: opcode=1010111, funct6=011000, funct3=101. Omit v0.t for vm=1 or include it for vm=0.
The mask destination may overlap v0. Reading the same register as mask and data with different EEWs is reserved. With LMUL=m1, vd may start at vs2.
Require valid vtype, enabled VS/FS, supported FP formats, and valid frm. With FLEN>SEW an invalid NaN box supplies canonical NaN; FLEN<SEW is reserved. Equality does not round by frm, but invalid frm use remains reserved.
Body is vstart≤i<vl; prestart is unchanged, inactive bits follow vma and mask tails are always agnostic. VL=0 or vstart≥vl updates no destination, including tails. The animation fixes LMUL=m1, VLEN=4096, vstart=0; steps are not processor cycles.
Common Usage Scenarios
Predicate mask generation
Assume enabled V/VS, supported e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; FS enabled, frm=RNE, FLEN=64, f0 validly NaN-boxed, unmasked. v2=[1.5,-0,2,1.5], f0=1.5 → v1.mask[0..3]=[1,0,0,1], NV unchanged. Tails are not guaranteed zero; mask destinations are always tail-agnostic.
FP condition testing
Assume enabled V/VS, supported e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; FS enabled, frm=RNE, FLEN=64, f0 validly NaN-boxed, unmasked. v2=[1.5,-0,2,1.5], f0=1.5 → v1.mask[0..3]=[1,0,0,1], NV unchanged. Tails are not guaranteed zero; mask destinations are always tail-agnostic.
NaN checks
Assume enabled V/VS, supported e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; FS enabled, frm=RNE, FLEN=64, f0 validly NaN-boxed, unmasked. v2=[1.5,-0,2,1.5], f0=1.5 → v1.mask[0..3]=[1,0,0,1], NV unchanged. Tails are not guaranteed zero; mask destinations are always tail-agnostic.
Vectorized conditional execution
Assume enabled V/VS, supported e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; FS enabled, frm=RNE, FLEN=64, f0 validly NaN-boxed, unmasked. v2=[1.5,-0,2,1.5], f0=1.5 → v1.mask[0..3]=[1,0,0,1], NV unchanged. Tails are not guaranteed zero; mask destinations are always tail-agnostic.
Pre-Use Checklist
Syntax Check
- vd is a single mask destination, one bit per element; rs1 selects an f register, not an integer register. Active elements write vs2[i]==f[rs1]; +0 equals -0, NaNs produce 0, and only active sNaN inputs raise NV.
- 32-bit OP-V: opcode=1010111, funct6=011000, funct3=101. Omit v0.t for vm=1 or include it for vm=0.
Semantic Check
- The mask destination may overlap v0. Reading the same register as mask and data with different EEWs is reserved. With LMUL=m1, vd may start at vs2.
- Require valid vtype, enabled VS/FS, supported FP formats, and valid frm. With FLEN>SEW an invalid NaN box supplies canonical NaN; FLEN<SEW is reserved. Equality does not round by frm, but invalid frm use remains reserved.
- Body is vstart≤i<vl; prestart is unchanged, inactive bits follow vma and mask tails are always agnostic. VL=0 or vstart≥vl updates no destination, including tails. The animation fixes LMUL=m1, VLEN=4096, vstart=0; steps are not processor cycles.
Pitfalls / Common Confusions
The result uses mask-register layout, one bit per element; it is not an ordinary integer vector of 0/-1 or 0/1 elements.
Compare instructions write a mask destination and treat tail elements as tail-agnostic; do not read tail bits as ordinary FP results.
With vm=0, v0.t is the execution mask; compare instructions allow the mask destination vd to overlap the source mask v0.
VMFEQ.VF uses scalar FP register f[rs1]; do not treat .vf rs1 as an integer GPR.
NaN and invalid-flag behavior follows the official RVV FP compare rules, not integer comparison or JavaScript comparison semantics.
FAQ
Can VMFEQ.VF write v0 when vm=0?
Yes. Mask-producing compares may overlap vd and source mask v0; ordinary masked vector instructions may not.
What result does VMFEQ.VF produce for NaN comparisons?
NaN comparisons write 0; only signaling NaNs raise invalid.