What does VMSGT.VI write?
Each active element writes mask bit i: 1 for true, 0 for false, not a SEW-wide integer.
VMSGT.VI
RISC-V VMSGT.VI Instruction Details
Instruction ManualOPIVIVMSGT.VI performs element-wise signed greater-than immediate comparison and writes active-element Boolean results to the destination mask.
Instruction Syntax
vmsgt.vi vd, vs2, imm[, v0.t]
Operand Breakdown
Syntax: vmsgt.vi vd, vs2, imm[, v0.t]; omit the mask for vm=1, include it for vm=0. The destination is one mask register with one bit per element, not SEW-wide integers.
Active elements perform two’s-complement signed greater-than comparison. imm is simm5 (-16..15), sign-extended to SEW before applying the instruction’s relation.
vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl. Prestart stays unchanged, inactive follows vma, mask tails are always agnostic; vl=0 or vstart≥vl updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0; steps are not processor cycles.
VVector IntegerCompare
Instruction Behavior
VMSGT.VI is a RISC-V V-extension vector-immediate integer predicate-generation instruction. Within the current vl body elements, it compares vs2[i] with the sign-extended 5-bit immediate; vm=1 lets all body elements participate, while vm=0 processes only elements selected by v0.t. The result is written to vd in mask-register layout, one bit per element index; integer compares do not set floating-point exception flags.
VMSGT.VI Decode And Execute Animation
Starts from OP-V encoding, then shows how signed integer greater than with immediate comparison reads active elements and produces a one-bit-per-element predicate mask.
Instruction input
vmsgt.vi
Execution context
Fixed legal teaching context: VLEN=4096 bits, LMUL=m1, and vstart=0; every selectable VL is within VLMAX=128 for the current SEW.
immediate value
7 -> 7
5-bit signed imm is sign-extended to SEWRequire valid vtype, enabled VS, and supported SEW. The destination may be v0 and, with LMUL=m1, may equal a data source. Equal data sources require equal elements; under v0.t, v0 cannot also be read as SEW data. Result tails are always agnostic; masked-off values follow vma. VL=0 updates nothing, including tails.
Destination overlap with a SEW data source forces ma/ta; x0/zero is always 0. Switching XLEN keeps low bits and zero-pads a valid raw pattern to the new width. Steps are teaching stages, not processor cycles.
V-format integer compare encoding
31..26
funct6
011111
25
vm
1
24..20
vs2
v8
19..15
imm
00111 (7)
14..12
funct3
011
11..7
vd
v0
6..0
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
3
2
7
7
0
12
5
9
>
>
>
>
>
>
>
>
>
imm
7
7
7
7
7
7
7
7
active
1
1
1
1
1
1
1
1
v0
-
-
-
-
-
-
-
-
This animation shows only the ISA-visible comparison, execution-mask, and destination-mask writeback relationship with vstart fixed at 0; inactive and tail elements are not simulated as fixed data values. For .vx, the selectable SEW values (8/16/32) do not exceed XLEN, so the model first takes the low SEW bits of x[rs1] and then applies this instruction's signed or unsigned relation.
Quick Understanding & Search Notes
VMSGT.VI does not write an ordinary integer vector; it writes each active element's signed greater-than immediate comparison result as one bit of the destination mask. The animation starts from OP-V encoding fields, decodes the vector-immediate operands, then shows per-lane comparison and vd.mask writeback.
32-bit OP-V: opcode=1010111, funct6=011111, funct3=011 (OPIVI). Omit v0.t for vm=1; include it for vm=0.
Active elements write vd bit i from vs2[i] > scalar: true gives 1, false 0. simm5 is -16..15 and is sign-extended to SEW. Compare in SEW-wide two’s-complement signed order.
vd is one mask register, independent of SEW/LMUL, and may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Body is vstart≤i<vl; prestart stays unchanged, inactive follows vma, mask tails are always agnostic. vl=0 or vstart≥vl updates no destination bits, including tails.
Vector Execution Context
Syntax: vmsgt.vi vd, vs2, imm[, v0.t]; omit the mask for vm=1, include it for vm=0. The destination is one mask register with one bit per element, not SEW-wide integers.
Active elements perform two’s-complement signed greater-than comparison. imm is simm5 (-16..15), sign-extended to SEW before applying the instruction’s relation.
vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl. Prestart stays unchanged, inactive follows vma, mask tails are always agnostic; vl=0 or vstart≥vl updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0; steps are not processor cycles.
Common Usage Scenarios
Conditional Execution
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0 and initialized sources; unmasked. v2=[0,1,7,15], imm=0 → v1.mask[0..3]=[0,1,1,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Range Check
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0 and initialized sources; unmasked. v2=[0,1,7,15], imm=0 → v1.mask[0..3]=[0,1,1,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmsgt.vi vd, vs2, imm[, v0.t]; omit the mask for vm=1, include it for vm=0. The destination is one mask register with one bit per element, not SEW-wide integers.
- Active elements perform two’s-complement signed greater-than comparison. imm is simm5 (-16..15), sign-extended to SEW before applying the instruction’s relation.
Semantic Check
- vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
- Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl. Prestart stays unchanged, inactive follows vma, mask tails are always agnostic; vl=0 or vstart≥vl updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0; steps are not processor cycles.
Pitfalls / Common Confusions
VMSGT.VI writes vd in mask-register layout, producing one predicate bit per element rather than SEW-wide integer results.
The immediate field is a 5-bit signed value; unsigned compares still sign-extend it to SEW first, then interpret that SEW bit pattern as unsigned.
With vm=0, only body elements selected by v0.t generate new results; mask-off and tail elements should not be taught as definitely writing zero.
FAQ
How does imm participate?
simm5 is -16..15 and is sign-extended to SEW. Compare in SEW-wide two’s-complement signed order.
How are v0.t and tails handled?
v0.t selects active body elements; mask tails are always agnostic. vl=0 leaves the destination unchanged.