What format does VMSLEU.VI produce?
The result is written in mask-register layout, one predicate bit per active element, not ordinary SEW-wide vector elements such as 0/1 or 0/-1.
VMSLEU.VI
RISC-V VMSLEU.VI Instruction Details
Instruction ManualOPIVIVMSLEU.VI performs element-wise unsigned less-or-equal immediate comparison and writes active-element Boolean results to the destination mask.
Instruction Syntax
vmsleu.vi vd, vs2, imm[, v0.t]
Operand Breakdown
Syntax: vmsleu.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=011100, funct3=011 (OPIVI).
Active elements compare vs2[i] <= scalar in unsigned order: true writes 1, false 0. simm5 (-16..15) is sign-extended to SEW first. At SEW=8, imm=-1 gives unsigned threshold 255.
vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
VVector IntegerCompare
Instruction Behavior
VMSLEU.VI is a RISC-V V-extension vector-immediate integer predicate-generation instruction. Within the current vl body elements, it compares vs2[i] and the 5-bit immediate sign-extended to SEW as unsigned bit patterns; vm=1 lets all body elements participate, while vm=0 processes only elements selected by v0.t. The result is written to vd in mask-register layout, one bit per element index.
VMSLEU.VI Decode And Execute Animation
Starts from OP-V encoding, then shows how unsigned integer less than or equal with immediate comparison reads active elements and produces a one-bit-per-element predicate mask.
Instruction input
vmsleu.vi
Execution context
Fixed legal teaching context: VLEN=4096 bits, LMUL=m1, and vstart=0; every selectable VL is within VLMAX=128 for the current SEW.
immediate value
7 -> 7
5-bit signed imm is sign-extended to SEWRequire valid vtype, enabled VS, and supported SEW. The destination may be v0 and, with LMUL=m1, may equal a data source. Equal data sources require equal elements; under v0.t, v0 cannot also be read as SEW data. Result tails are always agnostic; masked-off values follow vma. VL=0 updates nothing, including tails.
Legal destination overlap with a SEW data source forces ma/ta; steps are teaching stages, not processor cycles.
V-format integer compare encoding
31..26
funct6
011100
25
vm
1
24..20
vs2
v8
19..15
imm
00111 (7)
14..12
funct3
011
11..7
vd
v0
6..0
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
3
2
7
7
0
12
5
9
<=u
<=u
<=u
<=u
<=u
<=u
<=u
<=u
<=u
imm
7
7
7
7
7
7
7
7
active
1
1
1
1
1
1
1
1
v0
-
-
-
-
-
-
-
-
This animation shows only the ISA-visible comparison, execution-mask, and destination-mask writeback relationship with vstart fixed at 0; inactive and tail elements are not simulated as fixed data values. For .vx, the selectable SEW values (8/16/32) do not exceed XLEN, so the model first takes the low SEW bits of x[rs1] and then applies this instruction's signed or unsigned relation.
Quick Understanding & Search Notes
VMSLEU.VI does not write an ordinary integer vector; it writes each active element's unsigned less-or-equal immediate comparison result as one bit of the destination mask. The animation starts from OP-V encoding fields, decodes the vector-immediate operands, then shows per-lane comparison and vd.mask writeback.
32-bit OP-V: opcode=1010111, funct6=011100, funct3=011 (OPIVI). Omit v0.t for vm=1; include it for vm=0.
Active elements compare vs2[i] <= scalar in unsigned order, writing mask bit i as 1 for true and 0 for false. imm is simm5 (-16..15), sign-extended to SEW first. Unsigned thresholds are therefore 0..15 or 2^SEW−16..2^SEW−1; at SEW=8, imm=-1 means 255.
vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL, and vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Body is vstart≤i<vl; prestart stays unchanged, inactive follows vma, and mask tails are always agnostic. vl=0 or vstart≥vl updates no destination bits, including tails.
Vector Execution Context
Syntax: vmsleu.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=011100, funct3=011 (OPIVI).
Active elements compare vs2[i] <= scalar in unsigned order: true writes 1, false 0. simm5 (-16..15) is sign-extended to SEW first. At SEW=8, imm=-1 gives unsigned threshold 255.
vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
Common Usage Scenarios
Conditional Execution
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; the example is unmasked. v2=[0,1,0xffffffff,7], imm=0 → v1.mask[0..3]=[1,0,0,0]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Range Check
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; the example is unmasked. v2=[0,1,0xffffffff,7], imm=0 → v1.mask[0..3]=[1,0,0,0]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmsleu.vi vd, vs2, imm[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
- 32-bit OP-V: opcode=1010111, funct6=011100, funct3=011 (OPIVI).
Semantic Check
- Active elements compare vs2[i] <= scalar in unsigned order: true writes 1, false 0. simm5 (-16..15) is sign-extended to SEW first. At SEW=8, imm=-1 gives unsigned threshold 255.
- vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
- Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
Pitfalls / Common Confusions
VMSLEU.VI writes vd in mask-register layout, producing one predicate bit per element rather than SEW-wide integer results.
imm is simm5 (-16..15), sign-extended to SEW first. Unsigned thresholds are therefore 0..15 or 2^SEW−16..2^SEW−1; at SEW=8, imm=-1 means 255.
With vm=0, vs2 cannot also be v0: an encoding that reads v0 as both the EEW=1 execution mask and SEW-wide data source is reserved.
With vm=0, only body elements selected by v0.t generate new results; mask-off and tail elements should not be taught as definitely writing zero.
FAQ
How does the immediate participate in the compare?
imm is simm5 (-16..15), sign-extended to SEW first. Unsigned thresholds are therefore 0..15 or 2^SEW−16..2^SEW−1; at SEW=8, imm=-1 means 255.
Does vm or v0.t change the comparison relation?
No. vm only selects which body elements are active; active elements still use this instruction-specific comparison relation to generate mask bits.