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VMSLEU.VI

RISC-V VMSLEU.VI Instruction Details

Instruction ManualI-type

Perform element-wise <= comparison and write the Boolean result to mask destination vd.

Instruction Syntax

vmsleu.vi vd, vs2, imm, vm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
VVector IntegerCompare
Related Search Terms
VMSLEU.VI instructionRISC-V VMSLEU.VIvmsleu.vi syntaxvmsleu.vi RVVinteger comparemask result

Instruction Behavior

VMSLEU.VI is a RISC-V V vector integer unsigned less-or-equal compare instruction. For active elements within vl, it compares vs2 with a sign-extended 5-bit immediate and writes the comparison result to mask destination vd. The immediate is sign-extended to SEW before applying this instruction's comparison relation. Integer comparisons do not raise floating-point exceptions.

Quick Understanding & Search Notes

VMSLEU.VI produces mask bits, not a 0/-1 integer vector.

The destination stores Boolean results in mask-register layout, one bit per element.
Unsigned comparison determines the result; the immediate is sign-extended to SEW first.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Common Usage Scenarios

Conditional Execution

Understand this scenario with real code like «vmsleu.vi v1, v2, 0».

Range Check

Understand this scenario with real code like «vmsleu.vi v1, v2, 0».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Integer compares raise no FP exceptions
Result is always tail-agnostic
The unsigned compare immediate is not zero-extended; the 5-bit immediate is sign-extended to SEW first.

FAQ

Does VMSLEU.VI write ordinary vector elements?

No. Compare instructions write a mask destination vd, with one Boolean bit per element.

How does VMSLEU.VI handle masking?

With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.