What format does VMSLEU.VV produce?
One mask bit per active element: true writes 1, false writes 0. The result is not a SEW-wide integer vector.
VMSLEU.VV
RISC-V VMSLEU.VV Instruction Details
Instruction ManualOPIVVVMSLEU.VV performs element-wise unsigned less-or-equal comparison and writes active-element Boolean results to the destination mask.
Instruction Syntax
vmsleu.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vmsleu.vv vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=011100, funct3=000 (OPIVV).
Active elements compare vs2[i] <= vs1[i] in unsigned order: true writes 1, false 0. Equal data sources require equal initial elements.
vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 or vstart≥vl updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
VVector IntegerCompare
Instruction Behavior
VMSLEU.VV is a RISC-V V-extension vector-vector integer predicate-generation instruction. For each active body element (vstart <= i < vl), it compares vs2[i] with vs1[i]; vm=1 processes all body elements, while vm=0 processes only elements selected by v0.t. The result is written to vd in mask-register layout, one bit per element index.
VMSLEU.VV Decode And Execute Animation
Starts from OP-V encoding, then shows how unsigned integer less than or equal comparison reads active elements and produces a one-bit-per-element predicate mask.
Instruction input
vmsleu.vv
Execution context
Fixed legal teaching context: VLEN=4096 bits, LMUL=m1, and vstart=0; every selectable VL is within VLMAX=128 for the current SEW.
Require valid vtype, enabled VS, and supported SEW. The destination may be v0 and, with LMUL=m1, may equal a data source. Equal data sources require equal elements; under v0.t, v0 cannot also be read as SEW data. Result tails are always agnostic; masked-off values follow vma. VL=0 updates nothing, including tails.
Legal destination overlap with a SEW data source forces ma/ta; steps are teaching stages, not processor cycles.
V-format integer compare encoding
31..26
funct6
011100
25
vm
1
24..20
vs2
v8
19..15
vs1
v12
14..12
funct3
000
11..7
vd
v0
6..0
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
3
2
7
7
0
12
5
9
<=u
<=u
<=u
<=u
<=u
<=u
<=u
<=u
<=u
v12
3
4
6
7
1
8
5
10
active
1
1
1
1
1
1
1
1
v0
-
-
-
-
-
-
-
-
This animation shows only the ISA-visible comparison, execution-mask, and destination-mask writeback relationship with vstart fixed at 0; inactive and tail elements are not simulated as fixed data values. For .vx, the selectable SEW values (8/16/32) do not exceed XLEN, so the model first takes the low SEW bits of x[rs1] and then applies this instruction's signed or unsigned relation.
Quick Understanding & Search Notes
VMSLEU.VV does not write an ordinary integer vector; it writes each active element's unsigned less-or-equal comparison result as one bit of the destination mask. The animation starts from OP-V encoding fields, decodes the vector-vector operands, then shows per-lane comparison and vd.mask writeback.
The core semantic relation is vd.mask[i] = (unsigned(vs2[i]) <= unsigned(vs1[i])); only active body elements generate new destination mask bits.
32-bit OP-V: opcode=1010111, funct6=011100, funct3=000 (OPIVV).
vs2 and vs1 are interpreted at the current SEW; the comparison result is still a one-bit-per-element mask.
vm=0 uses v0.t to select active elements and vm=1 is unmasked; tail and mask-off elements are not forced to concrete values in the animation.
V 1.0 supports RV32/RV64; require enabled VS, valid vtype, and supported SEW. vd is one mask register and may be v0; legal different-EEW destination/source overlap forces ma/ta, and with vm=0 v0 cannot also supply SEW data.
Prestart remains unchanged; inactive follows vma, and mask tails are always agnostic. vl=0 or vstart≥vl updates no destination bits, including tails.
Vector Execution Context
Syntax: vmsleu.vv vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=011100, funct3=000 (OPIVV).
Active elements compare vs2[i] <= vs1[i] in unsigned order: true writes 1, false 0. Equal data sources require equal initial elements.
vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 or vstart≥vl updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
Common Usage Scenarios
Predicate Generation
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; the example is unmasked. v8=[0,2,7,9], v12=[0,2,6,10] → v0.mask[0..3]=[1,1,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Conditional Execution
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; the example is unmasked. v8=[0,2,7,9], v12=[0,2,6,10] → v0.mask[0..3]=[1,1,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Range Check
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; the example is unmasked. v8=[0,2,7,9], v12=[0,2,6,10] → v0.mask[0..3]=[1,1,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmsleu.vv vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
- 32-bit OP-V: opcode=1010111, funct6=011100, funct3=000 (OPIVV).
Semantic Check
- Active elements compare vs2[i] <= vs1[i] in unsigned order: true writes 1, false 0. Equal data sources require equal initial elements.
- vd may be v0. Different-EEW destination/source overlap must start at the source group’s lowest register and forces ma/ta. With vm=0, v0 cannot also supply SEW data.
- Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; body is vstart≤i<vl and prestart is unchanged. Inactive follows vma; mask tails are always agnostic. vl=0 or vstart≥vl updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
Pitfalls / Common Confusions
VMSLEU.VV writes vd in mask-register layout, producing one predicate bit per element rather than SEW-wide integer results.
vs2 and vs1 are interpreted at the current SEW; signed/unsigned affects only ordering comparisons, not the width of mask results.
With vm=0, only body elements selected by v0.t generate new results; mask-off and tail elements should not be taught as definitely writing zero.
FAQ
How do vs1 and vs2 participate in the compare?
Each active element computes vs2[i] <= vs1[i] in unsigned order: true writes 1, false writes 0. Equal source registers read the same initial values.
Does vm or v0.t change the comparison relation?
No. vm selects active body elements; it does not change the comparison relation.