Mask elements
Each element index maps to one predicate bit; this instruction operates on mask bits, not SEW-wide data elements.
VMOR.MM
RISC-V VMOR.MM Instruction Details
Instruction ManualV-typeVector mask OR: vd.mask[i] = vs2.mask[i] | vs1.mask[i]
Instruction Syntax
vmor.mm vd, vs2, vs1
Operand Breakdown
vd: destination mask register receiving a one-bit Boolean result per element.
vs2: first source mask register; element i supplies vs2.mask[i].
vs1: second source mask register; element i supplies vs1.mask[i]. `.mm` mask logical instructions are always unmasked and are not controlled by v0.t; vd can be any mask register, and only a result written or moved into v0 is later consumed through v0.t by ordinary masked vector instructions.
VVector OperationsMask Logic
Instruction Behavior
VMOR.MM is an RVV vector mask OR instruction. The `.mm` suffix means the sources and destination are mask-register operands; each mask element is one bit, and the instruction computes vd.mask[i] = vs2.mask[i] | vs1.mask[i] by element index. These instructions are always unmasked, vm=0 encodings are reserved, and tail elements are updated tail-agnostically.
VMOR.MM Decode And Execute Animation
Starts from V-extension encoding fields, then shows OR mask-logical field decode, mask-bit reads, per-lane execution, and vd writeback.
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Execution Context
V-format mask logical encoding
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v0
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This animation models only the ISA semantic relationship vd.mask[i] = vs2.mask[i] | vs1.mask[i]: read predicate bits from two mask registers, compute OR per lane, then write the destination mask register.
Quick Understanding & Search Notes
VMOR.MM is the vector mask OR member of the RVV mask-register logical instructions, used for predicate composition. The `.mm` suffix means vd, vs2, and vs1 have mask-register semantics; each element is one bit, independent of the current data SEW.
Operand semantics: vd can be any mask register and receives the result mask; vs2 and vs1 provide the two source masks. For element i, the Boolean formula is vd.mask[i] = vs2.mask[i] | vs1.mask[i].
A mask register holds one predicate bit per element index, not a SEW-wide data element; changing SEW changes ordinary data interpretation, but does not make one mask element SEW bits wide.
Mask logical instructions are always unmasked; they do not use v0.t to limit this instruction's execution, and vm=0 encodings are reserved. vd can be any mask register; only a result written or moved into v0 is later consumed through v0.t by ordinary masked vector instructions.
It combines two predicate masks into a union condition: the result bit is 1 when either source condition is true. C semantic analogy: maskC = (a > 0) || (b < 10); generate two comparison masks, then OR them bit by bit.
Typical workflow: compare instructions such as vmsgt/vmslt/vmseq first generate predicate masks, VMOR.MM then combines them with OR, and, when the composed result is in v0, a later maskable vector instruction consumes that mask through v0.t.
Vector Execution Context
When reading VMOR.MM, focus on bit-by-bit predicate composition in mask registers. .mm: sources and destination are mask registers, operating on one predicate bit per element.
.mm operands
vd can be any mask register receiving the result mask, while vs2 and vs1 provide the two source masks combined bit by bit at the same element index.
v0.t relation
Mask logical instructions are always unmasked; only a result written or moved into v0 is later consumed through v0.t by ordinary masked vector instructions.
Common Usage Scenarios
Predicate condition composition
Understand this scenario with real code like «vmor.mm v1, v2, v3».
Mask logical family comparison
Understand this scenario with real code like «vmor.mm v1, v2, v3».
Mask construction before masked execution
Understand this scenario with real code like «vmor.mm v1, v2, v3».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Assembly operand order is vd, vs2, vs1; ANDN/ORN invert vs1.
These mask logical instructions are always unmasked and vm=0 encodings are reserved; do not treat v0.t as this instruction's execution mask.
They operate on one-bit mask elements, not ordinary SEW-wide vector data elements; do not confuse them with vand/vor/vxor.
FAQ
What does the `.mm` suffix mean?
It means a mask-mask form: vd, vs2, and vs1 are interpreted as mask registers, operating on one predicate bit per element.
What is the Boolean formula for VMOR.MM?
The formula is vd.mask[i] = vs2.mask[i] | vs1.mask[i].
Is it controlled by the v0 mask?
No. Vector mask logical instructions are always unmasked and vm=0 encodings are reserved; vd can be any mask register. Only a result written or moved into v0 is later consumed through v0.t by ordinary masked vector instructions.
What condition does VMOR.MM express well?
It expresses the union of two predicates, such as lanes satisfying condition A or condition B.