Mask elements
Each element index maps to one predicate bit; this instruction operates on mask bits, not SEW-wide data elements.
VMNAND.MM
RISC-V VMNAND.MM Instruction Details
Instruction ManualV-typeVector mask NAND: vd.mask[i] = ~(vs2.mask[i] & vs1.mask[i])
Instruction Syntax
vmnand.mm vd, vs2, vs1
Operand Breakdown
vd: destination mask register receiving a one-bit Boolean result per element.
vs2: first source mask register; element i supplies vs2.mask[i].
vs1: second source mask register; element i supplies vs1.mask[i]. `.mm` mask logical instructions are always unmasked and are not controlled by v0.t; vd can be any mask register, and only a result written or moved into v0 is later consumed through v0.t by ordinary masked vector instructions.
VVector OperationsMask Logic
Instruction Behavior
VMNAND.MM is an RVV vector mask NAND instruction. The `.mm` suffix means the sources and destination are mask-register operands; each mask element is one bit, and the instruction computes vd.mask[i] = ~(vs2.mask[i] & vs1.mask[i]) by element index. These instructions are always unmasked, vm=0 encodings are reserved, and tail elements are updated tail-agnostically.
VMNAND.MM Decode And Execute Animation
Starts from V-extension encoding fields, then shows NAND mask-logical field decode, mask-bit reads, per-lane execution, and vd writeback.
vd
vs2
vs1
vmnand.mm
,
,
Execution Context
V-format mask logical encoding
31..26
25
24..20
19..15
14..12
11..7
6..0
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
NAND
~&
~&
~&
~&
~&
~&
~&
~&
~&
~&
~&
~&
~&
~&
~&
~&
v16
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
v0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
This animation fixes vstart=0 and models vd.mask[i] = ~(vs2.mask[i] & vs1.mask[i]) only for the shown VL body elements. Source rows show the original operand values used by the model; the specification permits vd to overlap either source. The final vd appears at Writeback, and successful completion leaves vstart at zero. The unshown mask tail is always tail-agnostic and may retain old bits, become 1s, or contain a result allowed by the specification, so the animation does not present a deterministic tail value.
Quick Understanding & Search Notes
VMNAND.MM applies bitwise NAND to two RVV mask registers: vd.mask[i] = ~(vs2.mask[i] & vs1.mask[i]). The `.mm` suffix means vd, vs2, and vs1 have mask-register semantics; the result is still a one-bit-per-element predicate mask, not ordinary SEW-wide data.
Operand semantics: vd can be any mask register and receives the result mask; vs2 and vs1 provide the two source masks. For element i, the Boolean formula is vd.mask[i] = ~(vs2.mask[i] & vs1.mask[i]).
A mask register holds one predicate bit per element index, not a SEW-wide data element; changing SEW changes ordinary data interpretation, but does not make one mask element SEW bits wide.
Mask logical instructions are always unmasked; they do not use v0.t to limit this instruction's execution, and vm=0 encodings are reserved. vd can be any mask register; only a result written or moved into v0 is later consumed through v0.t by ordinary masked vector instructions.
VMNAND.MM is the bitwise inverse of VMAND.MM: the result is 0 only when both vs2.mask[i] and vs1.mask[i] are 1, and 1 otherwise. C semantic analogy: maskC = !((a > 0) && (b < 10)); generate the two comparison masks first, then apply NAND bit by bit.
Typical workflow: compare instructions such as vmsgt/vmslt/vmseq first generate predicate masks, VMNAND.MM then combines them with NAND, and, when the composed result is in v0, a later maskable vector instruction consumes that mask through v0.t.
Vector Execution Context
When reading VMNAND.MM, focus on bit-by-bit predicate composition in mask registers. .mm: sources and destination are mask registers, operating on one predicate bit per element.
.mm operands
vd can be any mask register receiving the result mask, while vs2 and vs1 provide the two source masks combined bit by bit at the same element index.
v0.t relation
Mask logical instructions are always unmasked; only a result written or moved into v0 is later consumed through v0.t by ordinary masked vector instructions.
Common Usage Scenarios
Predicate condition composition
Understand this scenario with real code like «vmnand.mm v1, v2, v3».
Mask logical family comparison
Understand this scenario with real code like «vmnand.mm v1, v2, v3».
Mask construction before masked execution
Understand this scenario with real code like «vmnand.mm v1, v2, v3».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Assembly operand order is vd, vs2, vs1; ANDN/ORN invert vs1.
These mask logical instructions are always unmasked and vm=0 encodings are reserved; do not treat v0.t as this instruction's execution mask.
They operate on one-bit mask elements, not ordinary SEW-wide vector data elements; do not confuse them with vand/vor/vxor.
FAQ
What does the `.mm` suffix mean?
It means a mask-mask form: vd, vs2, and vs1 are interpreted as mask registers, operating on one predicate bit per element.
What is the Boolean formula for VMNAND.MM?
The formula is vd.mask[i] = ~(vs2.mask[i] & vs1.mask[i]).
Is it controlled by the v0 mask?
No. Vector mask logical instructions are always unmasked and vm=0 encodings are reserved; vd can be any mask register. Only a result written or moved into v0 is later consumed through v0.t by ordinary masked vector instructions.
How is VMNAND.MM related to VMAND.MM?
VMNAND.MM is the bitwise inverse of VMAND.MM, marking lanes where the two source predicates are not both true.
When is a VMNAND.MM result bit 0?
Only when both vs2.mask[i] and vs1.mask[i] are 1 for that lane. Every other input combination produces 1.