Is it the same as vand.vv/vor.vv?
No. Mask logical instructions operate on mask bits; vand/vor operate on normal vector data elements.
VMXNOR.MM
RISC-V VMXNOR.MM Instruction Details
Instruction ManualV-typeVector mask XNOR: vd.mask[i] = ~(vs2.mask[i] ^ vs1.mask[i])
Instruction Syntax
vmxnor.mm vd, vs2, vs1
Operand Breakdown
This is a V-type-format instruction. Confirm operand positions based on the assembly syntax.
VVector OperationsMask Logic
Instruction Behavior
VMXNOR.MM computes mask XNOR: vd.mask[i] = !(vs2.mask[i] ^ vs1.mask[i]), producing 1 where the two mask bits are equal.
Quick Understanding & Search Notes
VMXNOR.MM is the RVV vector mask XNOR instruction. It computes on one-bit mask elements with assembly operand order vd, vs2, vs1; mask logical instructions are always unmasked.
The operation is independent of data SEW/LMUL element width; sources and destination are mask values held in vector registers.
VMXNOR.MM's Boolean function must be read in vs2, vs1 order; this especially matters for ANDN/ORN.
Common Usage Scenarios
Mask Equality
Understand this scenario with real code like «vmxnor.mm v1, v2, v3».
Bit Match
Understand this scenario with real code like «vmxnor.mm v1, v2, v3».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Assembly operand order is vd, vs2, vs1; ANDN/ORN invert vs1.
These mask logical instructions are always unmasked; vm=0 encodings are reserved.
They operate on mask bits, not normal vector data elements; do not confuse them with vand/vor/vxor.
FAQ
Is it controlled by the v0 mask?
No. Vector mask logical instructions are always unmasked, with tail elements updated tail-agnostically.