How does VREV8.V use masking?
The optional assembly operand is v0.t: omit it for vm=1 or include it for vm=0. The masked destination vd must not overlap v0.
VREV8.V
RISC-V VREV8.V Instruction Details
Instruction ManualOP-V OPMVV (funct6=010010, vs1=01001, funct3=010)Vector byte-reverse: reverse byte order within each SEW element (endianness swap)
Instruction Syntax
vrev8.v vd, vs2, vm
Syntax: vrev8.v vd, vs2[, v0.t]. Vector registers select v0–v31. Omit v0.t for vm=1 or include it for vm=0. No immediate operand.
32-bit OP-V: funct6=010010, vm[25], vs2[24:20], 01001[19:15] (fixed selector), funct3=010, vd[11:7], opcode=1010111.
Zvbb or Zvkb depends on Zve32x and supports SEW=8/16/32, with 64 additionally requiring Zve64x. Reverse byte positions in each active element without changing bit order inside bytes.
Enable vector state with a legal supported vtype. Same-width sources/destination may overlap, reading original values; LMUL>1 groups must be aligned. With vm=0, vd must not overlap v0, which cannot supply both SEW data and an EEW=1 mask.
Only active body elements are processed. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements; successful execution resets vstart. Unsupported nonzero vstart may be rejected by the implementation.
ZvbbZvkbVector Bit Manipulation
Instruction Behavior
vrev8.v is provided by Zvbb or Zvkb and reverses byte order within each active SEW element. At SEW=32, 0x12345678 becomes 0x78563412; bit order within each byte is unchanged.
VREV8.V Decode & Execute Animation
This bounded model shows only lane 0 ISA-visible state; it does not model a pipeline, a cryptographic protocol, or unspecified inactive/tail values.
Execution context: enable the listed extension and vector state, use a legal supported vtype, LMUL=1 and VLEN≥64×SEW. Only lane 0 is expanded; vl=32/64 does not replicate it to other elements. SEW=64 requires Zve64x. Nonzero vstart assumes implementation support; otherwise an illegal-instruction exception is permitted.
Bounded execution context
32-bit OP-V encoding fields
31..26
funct6
010010
25
vm
1
24..20
vs2
01000
19..15
vs1 fixed
01001
14..12
funct3
010
11..7
vd
00100
6..0
OP-V
1010111
Execution data path
funct6=010010, funct3=010, Zvbb/Zvkb
v4[0] <- pending
Quick Understanding & Search Notes
Reverses byte order per element; at SEW=8, each element has one byte and its value is unchanged.
Reverses byte order within each SEW element without reversing bits inside bytes.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
Both Zvbb and Zvkb provide this instruction and depend on Zve32x: SEW=8/16/32; SEW=64 additionally requires Zve64x.
Body elements satisfy vstart≤i<vl; prestart is undisturbed and inactive/tail follow vma/vta. With vstart≥vl (including vl=0), all destination elements are undisturbed; success resets vstart=0.
vm=0 uses v0.t: vd must not be v0 and v0 cannot also be a SEW data source. Same-EEW data sources may overlap the destination. Nonzero vstart requires implementation support.
Vector Execution Context
Syntax: vrev8.v vd, vs2[, v0.t]. Vector registers select v0–v31. Omit v0.t for vm=1 or include it for vm=0. No immediate operand.
32-bit OP-V: funct6=010010, vm[25], vs2[24:20], 01001[19:15] (fixed selector), funct3=010, vd[11:7], opcode=1010111.
Zvbb or Zvkb depends on Zve32x and supports SEW=8/16/32, with 64 additionally requiring Zve64x. Reverse byte positions in each active element without changing bit order inside bytes.
Enable vector state with a legal supported vtype. Same-width sources/destination may overlap, reading original values; LMUL>1 groups must be aligned. With vm=0, vd must not overlap v0, which cannot supply both SEW data and an EEW=1 mask.
Only active body elements are processed. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements; successful execution resets vstart. Unsupported nonzero vstart may be rejected by the implementation.
Common Usage Scenarios
Crypto & Security
With the listed extension and vector state enabled, legal supported vtype, LMUL=1, VLEN=256, vstart=0 and no mask: SEW=32, vl=1, v8[0]=0x12345678: v4[0]=0x78563412. Only the active group/element is shown; tu keeps tails undisturbed. Success resets vstart=0.
Vector Acceleration
With the listed extension and vector state enabled, legal supported vtype, LMUL=1, VLEN=256, vstart=0 and no mask: SEW=32, vl=1, v8[0]=0x12345678: v4[0]=0x78563412. Only the active group/element is shown; tu keeps tails undisturbed. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vrev8.v vd, vs2[, v0.t]. Vector registers select v0–v31. Omit v0.t for vm=1 or include it for vm=0. No immediate operand.
- 32-bit OP-V: funct6=010010, vm[25], vs2[24:20], 01001[19:15] (fixed selector), funct3=010, vd[11:7], opcode=1010111.
Semantic Check
- Zvbb or Zvkb depends on Zve32x and supports SEW=8/16/32, with 64 additionally requiring Zve64x. Reverse byte positions in each active element without changing bit order inside bytes.
- Enable vector state with a legal supported vtype. Same-width sources/destination may overlap, reading original values; LMUL>1 groups must be aligned. With vm=0, vd must not overlap v0, which cannot supply both SEW data and an EEW=1 mask.
- Only active body elements are processed. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements; successful execution resets vstart. Unsupported nonzero vstart may be rejected by the implementation.
Pitfalls / Common Confusions
Reverses byte order, not bit order within bytes. Orthogonal to vbrev8.v.
FAQ
What determines the element width for VREV8.V?
A legal, supported vtype.SEW selects 8, 16 or 32 bits with Zve32x; 64 bits additionally requires Zve64x.