Is VSEXT.VF2 zero extension?
No. VSEXT performs sign extension; zero extension uses VZEXT.VF2/VF4/VF8.
VSEXT.VF2
RISC-V VSEXT.VF2 Instruction Details
Instruction ManualR-typeSign-extend SEW/2 source elements to SEW destination elements.
Instruction Syntax
vsext.vf2 vd, vs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector IntegerSign-Extend
Related Search Terms
Instruction Behavior
VSEXT.VF2 reads narrower signed source elements, sign-extends them to the current SEW width, and writes vd.
Quick Understanding & Search Notes
VSEXT.VF2 promotes a narrow signed integer vector to the current SEW.
Source element width is SEW/2; destination element width is SEW.
The sign bit is extended into the high bits; use VZEXT for unsigned extension.
The destination/source EEW ratio affects legal register-group overlap.
Common Usage Scenarios
Narrow Data Widening
Understand this scenario with real code like «vsext.vf2 v8, v12, v0.t».
Type Promotion
Understand this scenario with real code like «vsext.vf2 v8, v12, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Source EMUL=LMUL/2; can be fractional
Sign bit fill (differs from vzext zero-fill)