What determines the element count for vzext.vf8?
Body elements satisfy vstart≤i<vl; only mask-enabled elements perform the extension. SEW and LMUL determine widths and register grouping; vma/vta govern permitted inactive/tail results.
VZEXT.VF8
RISC-V VZEXT.VF8 Instruction Details
Instruction ManualOPMVVVZEXT.VF8 zero-extends EEW=SEW/8 source elements into SEW-wide destination elements.
Instruction Syntax
vzext.vf8 vd, vs2, vm
Operand Breakdown
vd: EEW=SEW, EMUL=LMUL. vs2 is the only data source, with EEW=SEW/8 and EMUL=LMUL/8. Unsupported source EEW or source EMUL below the minimum legal LMUL makes the encoding reserved.
32-bit OP-V: opcode=1010111, funct6=010010, funct3=010 (OPMVV). vm is bit25, vs2 bits24:20, VXUNARY0 selector=00010 bits19:15, and vd bits11:7. vm is not a numeric assembly operand: optional v0.t means vm=0; omission means vm=1.
For each active element, copy the SEW/8-bit source into the destination low bits and fill upper bits with zero. There is no vs1 data operand or floating-point conversion.
A wider destination may overlap a narrow source only when source EMUL>=1 and the source occupies its highest end; legal different-EEW overlap forces mask/tail-agnostic behavior. At the animation's LMUL=m1, source EMUL<1, so vd and vs2 must differ. Register groups align to EMUL. Ordinary masked vd excludes v0, which cannot supply both an EEW=1 mask and data.
Require V 1.0, enabled vector state, vill=0, and support for selected SEW/EEW and EMUL. Active elements satisfy vstart<=i<vl with masking enabled. Prestart stays unchanged; inactive/tail follow vma/vta, allowing old values or all ones. vstart>=vl (including vl=0) updates no destination elements; success resets vstart=0. The animation fixes VLEN=4096, LMUL=m1, vstart=0; stages are not processor cycles.
VVector Operations
Instruction Behavior
vzext.vf8 is a RISC-V V-extension vector integer zero-extension instruction. Syntax is `vzext.vf8 vd, vs2, vm`: active vs2 elements are read at EEW=SEW/8 and written as SEW-wide vd elements. Source EMUL is (EEW/SEW)*LMUL; the encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL.
VZEXT.VF8 Decode And Execute Animation
Official V-extension integer zero/sign extension from EEW to SEW.
Current step
Show the OP-V encoding
The strip shows opcode, funct6, the VXUNARY0 selector, register fields, and vm.
Live data pathencoding
OP-V
32-bit instruction fields
32-bit instruction fields
→
await read/execute
→
await result
Syntax: vd, vs2, vm
EEW
8 (SEW/8)
8 (SEW/8)
LMUL
m1 (fixed)
m1 (fixed)
VLEN
4096 bits
4096 bits
vstart
0
0
funct6
010010vm
0vs2 [24:20]
01100vs1 / VXUNARY0
00010funct3
010vd [11:7]
01000opcode
1010111
010010vm
0vs2 [24:20]
01100vs1 / VXUNARY0
00010funct3
010vd [11:7]
01000opcode
1010111
lane 0
vs2: 0x01
waiting
vs2: 0x01
waiting
lane 1
vs2: 0x83
masked-off
vs2: 0x83
masked-off
lane 2
vs2: 0x07
waiting
vs2: 0x07
waiting
lane 3
vs2: 0x7F
waiting
vs2: 0x7F
waiting
Based on The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture. The teaching context assumes enabled V/vector state, valid vtype, and that the selected SEW/EEW values are supported by the implementation and fixes VLEN=4096, LMUL=m1, and vstart=0; VLMAX=4096/SEW, so the animation's maximum VL of 64 does not exceed VLMAX. The encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL; this animation assumes supported SEW/EEW and fractional LMUL for every offered choice. Steps explain the ISA, not hardware cycles.
Quick Understanding & Search Notes
vzext.vf8 processes only active elements within vl: it zero-extends EEW=SEW/8 vs2 elements into SEW-wide vd elements; optional v0.t permits only mask-selected body elements to execute.
Official syntax is `vzext.vf8 vd, vs2, vm`. It has no second vector arithmetic source; the VXUNARY0 selector in the encoding is not an assembly syntax operand.
Source EEW=SEW/8 and source EMUL=(EEW/SEW)*LMUL; destination EEW=SEW and destination EMUL=LMUL. The encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL.
Each active result places the source bit pattern in the low EEW bits and fills all remaining upper bits with zero.
Vector Execution Context
vd: EEW=SEW, EMUL=LMUL. vs2 is the only data source, with EEW=SEW/8 and EMUL=LMUL/8. Unsupported source EEW or source EMUL below the minimum legal LMUL makes the encoding reserved.
32-bit OP-V: opcode=1010111, funct6=010010, funct3=010 (OPMVV). vm is bit25, vs2 bits24:20, VXUNARY0 selector=00010 bits19:15, and vd bits11:7. vm is not a numeric assembly operand: optional v0.t means vm=0; omission means vm=1.
For each active element, copy the SEW/8-bit source into the destination low bits and fill upper bits with zero. There is no vs1 data operand or floating-point conversion.
A wider destination may overlap a narrow source only when source EMUL>=1 and the source occupies its highest end; legal different-EEW overlap forces mask/tail-agnostic behavior. At the animation's LMUL=m1, source EMUL<1, so vd and vs2 must differ. Register groups align to EMUL. Ordinary masked vd excludes v0, which cannot supply both an EEW=1 mask and data.
Require V 1.0, enabled vector state, vill=0, and support for selected SEW/EEW and EMUL. Active elements satisfy vstart<=i<vl with masking enabled. Prestart stays unchanged; inactive/tail follow vma/vta, allowing old values or all ones. vstart>=vl (including vl=0) updates no destination elements; success resets vstart=0. The animation fixes VLEN=4096, LMUL=m1, vstart=0; stages are not processor cycles.
Common Usage Scenarios
Vector Integer Extension
Assume enabled V 1.0/vector state, valid supported e64,m1,tu,mu, VLEN=4096, vstart=0, supported source 8-bit EEW and fractional EMUL, and initialized sources/v0. vsetivli requests AVL=4, giving vl=4; v0.mask[0..3]=1011. vs2[0]=0x83 → vd[0]=0x0000000000000083; inactive lane1 and tails keep old destination values.
EEW-to-SEW extension
Assume enabled V 1.0/vector state, valid supported e64,m1,tu,mu, VLEN=4096, vstart=0, supported source 8-bit EEW and fractional EMUL, and initialized sources/v0. vsetivli requests AVL=4, giving vl=4; v0.mask[0..3]=1011. vs2[0]=0x83 → vd[0]=0x0000000000000083; inactive lane1 and tails keep old destination values.
V standard vector extension
Assume enabled V 1.0/vector state, valid supported e64,m1,tu,mu, VLEN=4096, vstart=0, supported source 8-bit EEW and fractional EMUL, and initialized sources/v0. vsetivli requests AVL=4, giving vl=4; v0.mask[0..3]=1011. vs2[0]=0x83 → vd[0]=0x0000000000000083; inactive lane1 and tails keep old destination values.
Pre-Use Checklist
Syntax Check
- vd: EEW=SEW, EMUL=LMUL. vs2 is the only data source, with EEW=SEW/8 and EMUL=LMUL/8. Unsupported source EEW or source EMUL below the minimum legal LMUL makes the encoding reserved.
- 32-bit OP-V: opcode=1010111, funct6=010010, funct3=010 (OPMVV). vm is bit25, vs2 bits24:20, VXUNARY0 selector=00010 bits19:15, and vd bits11:7. vm is not a numeric assembly operand: optional v0.t means vm=0; omission means vm=1.
Semantic Check
- For each active element, copy the SEW/8-bit source into the destination low bits and fill upper bits with zero. There is no vs1 data operand or floating-point conversion.
- A wider destination may overlap a narrow source only when source EMUL>=1 and the source occupies its highest end; legal different-EEW overlap forces mask/tail-agnostic behavior. At the animation's LMUL=m1, source EMUL<1, so vd and vs2 must differ. Register groups align to EMUL. Ordinary masked vd excludes v0, which cannot supply both an EEW=1 mask and data.
- Require V 1.0, enabled vector state, vill=0, and support for selected SEW/EEW and EMUL. Active elements satisfy vstart<=i<vl with masking enabled. Prestart stays unchanged; inactive/tail follow vma/vta, allowing old values or all ones. vstart>=vl (including vl=0) updates no destination elements; success resets vstart=0. The animation fixes VLEN=4096, LMUL=m1, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
This form reads EEW=SEW/8 source elements, not SEW-wide ones; only the destination elements are SEW wide.
Zero extension fills upper bits with zero; use the matching vsext form when the source sign bit must be preserved.
Masked-off and tail element values follow the current vtype mask/tail policy; the mnemonic does not imply fixed zeroing.
FAQ
Does vzext.vf8 always process the whole vector register?
No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.