Does VSHA2MS.VV support vm masking?
No. The official syntax has no vm operand.
VSHA2MS.VV
RISC-V VSHA2MS.VV Instruction Details
Instruction ManualR-typeVector SHA-2 message schedule expansion producing the next four message words; Zvknha uses SEW=32 and Zvknhb supports SEW=32/64.
Instruction Syntax
vsha2ms.vv vd, vs2, vs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvknhaZvknhbVector CryptoSHA-256
Instruction Behavior
VSHA2MS.VV is a vector SHA-2 element-group instruction. It computes the next message-schedule words from the words held in vd, vs2, and vs1. Under Zvknha SEW must be 32; under Zvknhb SEW may be 32 or 64.
Quick Understanding & Search Notes
VSHA2MS.VV is a vector SHA-2 element-group instruction, not an ordinary per-element arithmetic operation and not a v0.t-masked operation.
SEW=32 corresponds to SHA-256; SEW=64 corresponds to SHA-512 and requires Zvknhb.
Register-group overlap restrictions are part of encoding legality.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vsha2ms.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vsha2ms.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
The vd register group must not overlap vs1 or vs2.
SHA-2 uses EGS=4; vl and vstart must be aligned to element groups.
Software must handle SHA-2 big-endian message/final-hash byte ordering as required by the algorithm.
FAQ
How is SEW selected for VSHA2MS.VV?
It comes from current vtype, but must satisfy the Zvknha/Zvknhb SEW restrictions.