Does VSHA2MS.VV support vm masking?
No. The official syntax has no vm operand.
VSHA2MS.VV
RISC-V VSHA2MS.VV Instruction Details
Instruction ManualV-type (OP-VE / OPMVV)Vector SHA-2 message schedule expansion producing the next four message words; Zvknha uses SEW=32 and Zvknhb supports SEW=32/64.
Instruction Syntax
vsha2ms.vv vd, vs2, vs1
Syntax: vsha2ms.vv vd, vs2, vs1; v0–v31 are vector registers; no immediate. Fixed vm=1; no v0.t masking.
32-bit OP-VE: funct6=101101[31:26], vm=1[25], vs2[24:20], vs1[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Zvknha depends on Zve32x, supporting only SEW=32 (SHA-256); Zvknhb depends on Zve64x, supporting SEW=32/64 (SHA-256/SHA-512). vd={W3,W2,W1,W0}, vs2={W11,W10,W9,W4}, vs1={W15,W14,unused,W12}; generate W16–W19 in vd. Software byte-swaps initial message words; subsequent schedule words need no swap. Braces run from highest to lowest element index.
EGS=4, EGW=4*SEW. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap either vs1 or vs2 group. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
ZvknhaZvknhbVector CryptoSHA-2
Instruction Behavior
Compute the next four SHA-2 schedule words. Zvknha supports SEW=32; Zvknhb supports SEW=32/64. vd is both input and output.
VSHA2MS.VV Decode & Execute Animation
This bounded model shows official ISA-visible data flow for one element group; it does not model a cryptographic protocol or microarchitecture.
vsha2ms.vv
Fixed vm=1, OP-VE, OPMVV; EGS=4, EGW=128.
Lists below run from low to high element index; only the active group is shown and tu preserves tails. vd[0..3]=[0,1,2,3]; vs2[0..3]=[4,9,10,11]; vs1[0..3]=[12,13,14,15]. Values are SHA message words after software endian conversion.
funct6=101101vm=1vs2=01000vs1=01100OPMVV=010vd=00100OP-VE=1110111
Execution data path
OP-VE -> funct6 101101 -> vsha2ms.vv
result pending
Quick Understanding & Search Notes
VSHA2MS.VV is a vector SHA-2 element-group instruction, not an ordinary per-element arithmetic operation and not a v0.t-masked operation.
SEW=32 corresponds to SHA-256; SEW=64 corresponds to SHA-512 and requires Zvknhb.
Register-group overlap restrictions are part of encoding legality.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 33: Vector Cryptography Extensions, Version 1.0The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31: V Standard Extension for Vector Operations, Version 1.0
Vector Execution Context
Syntax: vsha2ms.vv vd, vs2, vs1; v0–v31 are vector registers; no immediate. Fixed vm=1; no v0.t masking.
32-bit OP-VE: funct6=101101[31:26], vm=1[25], vs2[24:20], vs1[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Zvknha depends on Zve32x, supporting only SEW=32 (SHA-256); Zvknhb depends on Zve64x, supporting SEW=32/64 (SHA-256/SHA-512). vd={W3,W2,W1,W0}, vs2={W11,W10,W9,W4}, vs1={W15,W14,unused,W12}; generate W16–W19 in vd. Software byte-swaps initial message words; subsequent schedule words need no swap. Braces run from highest to lowest element index.
EGS=4, EGW=4*SEW. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap either vs1 or vs2 group. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
Common Usage Scenarios
Crypto & Security
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=4, vstart=0 and tu. Initialize the input groups named in the syntax. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Vector Acceleration
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=4, vstart=0 and tu. Initialize the input groups named in the syntax. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vsha2ms.vv vd, vs2, vs1; v0–v31 are vector registers; no immediate. Fixed vm=1; no v0.t masking.
- 32-bit OP-VE: funct6=101101[31:26], vm=1[25], vs2[24:20], vs1[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Semantic Check
- Zvknha depends on Zve32x, supporting only SEW=32 (SHA-256); Zvknhb depends on Zve64x, supporting SEW=32/64 (SHA-256/SHA-512). vd={W3,W2,W1,W0}, vs2={W11,W10,W9,W4}, vs1={W15,W14,unused,W12}; generate W16–W19 in vd. Software byte-swaps initial message words; subsequent schedule words need no swap. Braces run from highest to lowest element index.
- EGS=4, EGW=4*SEW. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap either vs1 or vs2 group. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
- Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
The vd register group must not overlap vs1 or vs2.
SHA-2 uses EGS=4; vl and vstart must be aligned to element groups.
Software byte-swaps the first 16 big-endian message words; subsequent schedule words produced by this instruction need no further byte swap.
FAQ
How is SEW selected for VSHA2MS.VV?
It comes from current vtype, but must satisfy the Zvknha/Zvknhb SEW restrictions.