Does VSHA2CH.VV support vm masking?
No. The official syntax has no vm operand.
VSHA2CH.VV
RISC-V VSHA2CH.VV Instruction Details
Instruction ManualVector OP-VE (OPMVV)Vector two SHA-2 compression rounds using state groups and message-schedule constants; Zvknha uses SEW=32 and Zvknhb supports SEW=32/64.
Instruction Syntax
vsha2ch.vv vd, vs2, vs1
Syntax: vsha2ch.vv vd, vs2, vs1; vector registers select v0–v31. There is no immediate. Fixed vm=1 means unmasked; vd is both input and output.
32-bit OP-VE: funct6=101110[31:26], fixed vm=1[25], vs2[24:20], vs1[19:15], funct3=010, vd[11:7], opcode=1110111.
Zvknha depends on Zve32x and supports only SEW=32 (SHA-256); Zvknhb depends on Zve64x and supports SEW=32/64 (SHA-256/SHA-512). vd={c,d,g,h}, vs2={a,b,e,f}; vs1's high pair [3:2] supplies W0 (lower selected word), then W1 (higher selected word). After two rounds, only next {a,b,e,f} is written to vd; latency must be data-independent.
EGS=4 and EGW=4*SEW. vl/vstart not divisible by 4, unsupported extension/SEW combinations or vd overlap with either source group are reserved. LMUL*VLEN<EGW raises an illegal-instruction exception even at vl=0. Groups follow LMUL alignment; equal source registers read equal inputs.
Enable vector state with a legal supported vtype. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support, otherwise an illegal-instruction exception is permitted.
ZvknhaZvknhbVector CryptoSHA-2
Instruction Behavior
VSHA2CH.VV is a vector SHA-2 element-group instruction. It performs two compression rounds using current state in vd and vs2 plus message-schedule/constant data in vs1; vd is both input and output. Under Zvknha SEW must be 32; under Zvknhb SEW may be 32 or 64. This form selects the high pair vs1[3:2], consuming the lower selected word first.
VSHA2CH.VV Decode & Execute Animation
This bounded model expands two ISA-visible SHA-2 rounds for one element group; it does not model a hash protocol, byte-order conversion process, or microarchitecture.
Execution context: enable the selected extension and vector state with legal supported vtype, LMUL=1; the normal branch has VLEN≥8×SEW. Only group 0 is expanded, with element 0 in the low SEW bits. The insufficient-capacity branch represents LMUL*VLEN<4×SEW. Nonzero vstart assumes implementation support; equal source registers require equal input groups.
31..26
funct6
101110
25
vm fixed
1
24..20
vs2
01000
19..15
vs1
01100
14..12
OPMVV
010
11..7
vd
00100
6..0
OP-VE
1110111
OP-VE OPMVV, funct6=101110, vm=1, Zvknha
v4[0..3] <- pending
Quick Understanding & Search Notes
VSHA2CH.VV is a vector SHA-2 element-group instruction, not an ordinary per-element arithmetic operation and not a v0.t-masked operation.
SEW=32 corresponds to SHA-256; SEW=64 corresponds to SHA-512 and requires Zvknhb.
Register-group overlap restrictions are part of encoding legality.
vd reads {c,d,g,h}, vs2 reads {a,b,e,f}; the high pair vs1[3:2] supplies two message-schedule-plus-constant words, and vd receives next {a,b,e,f}.
EGS=4 and EGW=4*SEW. vl/vstart not divisible by 4 is reserved; LMUL*VLEN<EGW raises an illegal-instruction exception even at vl=0.
Available in Zvknha or Zvknhb, depending on Zve32x or Zve64x respectively. Execution latency must be data-independent.
Vector Execution Context
Syntax: vsha2ch.vv vd, vs2, vs1; vector registers select v0–v31. There is no immediate. Fixed vm=1 means unmasked; vd is both input and output.
32-bit OP-VE: funct6=101110[31:26], fixed vm=1[25], vs2[24:20], vs1[19:15], funct3=010, vd[11:7], opcode=1110111.
Zvknha depends on Zve32x and supports only SEW=32 (SHA-256); Zvknhb depends on Zve64x and supports SEW=32/64 (SHA-256/SHA-512). vd={c,d,g,h}, vs2={a,b,e,f}; vs1's high pair [3:2] supplies W0 (lower selected word), then W1 (higher selected word). After two rounds, only next {a,b,e,f} is written to vd; latency must be data-independent.
EGS=4 and EGW=4*SEW. vl/vstart not divisible by 4, unsupported extension/SEW combinations or vd overlap with either source group are reserved. LMUL*VLEN<EGW raises an illegal-instruction exception even at vl=0. Groups follow LMUL alignment; equal source registers read equal inputs.
Enable vector state with a legal supported vtype. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support, otherwise an illegal-instruction exception is permitted.
Common Usage Scenarios
Crypto & Security
Enable the listed extension and vector state with legal supported vtype, LMUL=1, VLEN=256, vstart=0 and no mask: SEW=32, vl=4, v4={c,d,g,h}=0, v8={a,b,e,f}=0, v12=0: T1=T2=0 in both rounds; v4={a,b,e,f}=0. Only active elements/groups are shown; tu keeps tails undisturbed. Success resets vstart=0.
Vector Acceleration
Enable the listed extension and vector state with legal supported vtype, LMUL=1, VLEN=256, vstart=0 and no mask: SEW=32, vl=4, v4={c,d,g,h}=0, v8={a,b,e,f}=0, v12=0: T1=T2=0 in both rounds; v4={a,b,e,f}=0. Only active elements/groups are shown; tu keeps tails undisturbed. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vsha2ch.vv vd, vs2, vs1; vector registers select v0–v31. There is no immediate. Fixed vm=1 means unmasked; vd is both input and output.
- 32-bit OP-VE: funct6=101110[31:26], fixed vm=1[25], vs2[24:20], vs1[19:15], funct3=010, vd[11:7], opcode=1110111.
Semantic Check
- Zvknha depends on Zve32x and supports only SEW=32 (SHA-256); Zvknhb depends on Zve64x and supports SEW=32/64 (SHA-256/SHA-512). vd={c,d,g,h}, vs2={a,b,e,f}; vs1's high pair [3:2] supplies W0 (lower selected word), then W1 (higher selected word). After two rounds, only next {a,b,e,f} is written to vd; latency must be data-independent.
- EGS=4 and EGW=4*SEW. vl/vstart not divisible by 4, unsupported extension/SEW combinations or vd overlap with either source group are reserved. LMUL*VLEN<EGW raises an illegal-instruction exception even at vl=0. Groups follow LMUL alignment; equal source registers read equal inputs.
- Enable vector state with a legal supported vtype. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support, otherwise an illegal-instruction exception is permitted.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
The vd register group must not overlap vs1 or vs2.
SHA-2 uses EGS=4; vl and vstart must be aligned to element groups.
This instruction treats words as little-endian; after all message blocks, convert final hash words to the standard big-endian byte order.
FAQ
How is SEW selected for VSHA2CH.VV?
It comes from current vtype, but must satisfy the Zvknha/Zvknhb SEW restrictions.