What unit do VSOXEI8.V indexes use?
Index values are unsigned byte offsets, not element numbers.
VSOXEI8.V
RISC-V VSOXEI8.V Instruction Details
Instruction ManualV-typeUse x[rs1] plus 8-bit unsigned byte offsets from vs2 for ordered indexed stores from active vs3 elements.
Instruction Syntax
vsoxei8.v vs3, (rs1), vs2, vm
Operand Breakdown
V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
Data EEW=SEW, EMUL=LMUL; index EMUL=(index EEW/SEW)*LMUL must be 1/8..8. Groups align; one register cannot provide different source EEWs, including EEW=1 v0. Inactive/tail make no access; vstart>=vl makes no access.
Unsigned byte indexes zero-extend when narrower than XLEN and are not scaled by data width. Ordered stores obey RVWMO at element level. Sources remain unchanged; active accesses may trap, and misaligned accesses may succeed or fault.
VVector MemoryIndexed Vector Store
Instruction Behavior
VSOXEI8.V is an RISC-V V-extension ordered indexed vector store instruction. Each active element forms its address as x[rs1] + zero_extend(vs2[i]) and stores the current-SEW data from vs3[i]; ei8 specifies only the index EEW. The ordered form writes elements to memory in element order and obeys RVWMO at the element level. With vm=0, elements disabled by v0.t do not write memory.
VSOXEI8.V Decode And Execute Animation
Decode the 8-bit indexed store, then compute each element address as x[rs1] + zero_extend(vs2[i]).
Instruction input
vsoxei8.v
Execution Context
Execution context: index EEW=8, data SEW=32, index EEW=8 is narrower than XLEN=64, so it is zero-extended before addition, ordered indexed accesses proceed in element order and obey RVWMO at the element level, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW/index EEW; fix VLEN=4096, LMUL=m1, vstart=0, VLMAX=4096/32, index EMUL=0.25. Index groups align and stay within v31; a register cannot supply different source EEWs, and v0.t excludes v0 data sources. Equal-EEW vs3/vs2 sharing a register require equal elements. x0 gives base zero. Assume all active accesses succeed; misaligned accesses require environment support. The address display range 0..0xffffffff is a teaching limit, not an ISA limit. Rows show per-element store events, not a final byte-memory image; later overlapping stores may overwrite earlier data. Ordered stores obey RVWMO in element order. Stages are not processor cycles. Inactive/tail elements make no access; VL=0 makes no access. Sources remain unchanged; success resets vstart=0.
Encoding fieldsvsoxei8.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
11
25
vm
0
24..20
vs2
00100
19..15
rs1
01010
14..12
width
000
11..7
vd/vs3
01100
6..0
opcode
0100111
Address and data pathaddr[i] = 0x8000 + zero_extend(vs2[i])
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x01
0x04
0x07
0x0a
0x0d
0x10
0x13
0x16
0x19
0x1c
0x1f
0x22
0x25
0x28
0x2b
0x2e
addr
0x8001
0x8004
0x8007
0x800a
0x800d
0x8010
0x8013
0x8016
0x8019
0x801c
0x801f
0x8022
0x8025
0x8028
0x802b
0x802e
v12
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
...
...
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...
...
...
...
-
...
...
...
...
-
...
...
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Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VSOXEI8.V is an RVV ordered indexed store; memory writes occur only for active elements not masked off.
The ei8 in the mnemonic is the index EEW, and index values are unsigned byte offsets.
Ordered indexed stores preserve observable element-store order.
vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=11, width=000; vm selects masking, with vs2/rs1/vs3 at bits24:20, 19:15, 11:7.
Vector Execution Context
V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
Data EEW=SEW, EMUL=LMUL; index EMUL=(index EEW/SEW)*LMUL must be 1/8..8. Groups align; one register cannot provide different source EEWs, including EEW=1 v0. Inactive/tail make no access; vstart>=vl makes no access.
Unsigned byte indexes zero-extend when narrower than XLEN and are not scaled by data width. Ordered stores obey RVWMO at element level. Sources remain unchanged; active accesses may trap, and misaligned accesses may succeed or fault.
Common Usage Scenarios
Ordered indirect writes
Assume enabled V/VS, valid supported vtype, LMUL=m1, VLEN=4096, XLEN=64, vstart=0, initialized sources and all body mask bits enabled. SEW=32, vl=4, a0=0x8000, v4=[0,4,8,12], v8=[10,20,30,40] → stores [0x8000]=10, [0x8004]=20, [0x8008]=30, [0x800C]=40. Assume writable memory and successful accesses; sources stay unchanged and inactive/tail make no access. Success resets vstart=0.
Device or side-effecting address spaces
Assume enabled V/VS, valid supported vtype, LMUL=m1, VLEN=4096, XLEN=64, vstart=0, initialized sources and all body mask bits enabled. SEW=32, vl=4, a0=0x8000, v4=[0,4,8,12], v8=[10,20,30,40] → stores [0x8000]=10, [0x8004]=20, [0x8008]=30, [0x800C]=40. Assume writable memory and successful accesses; sources stay unchanged and inactive/tail make no access. Success resets vstart=0.
Sparse table updates
Assume enabled V/VS, valid supported vtype, LMUL=m1, VLEN=4096, XLEN=64, vstart=0, initialized sources and all body mask bits enabled. SEW=32, vl=4, a0=0x8000, v4=[0,4,8,12], v8=[10,20,30,40] → stores [0x8000]=10, [0x8004]=20, [0x8008]=30, [0x800C]=40. Assume writable memory and successful accesses; sources stay unchanged and inactive/tail make no access. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
- Data EEW=SEW, EMUL=LMUL; index EMUL=(index EEW/SEW)*LMUL must be 1/8..8. Groups align; one register cannot provide different source EEWs, including EEW=1 v0. Inactive/tail make no access; vstart>=vl makes no access.
Semantic Check
- Unsigned byte indexes zero-extend when narrower than XLEN and are not scaled by data width. Ordered stores obey RVWMO at element level. Sources remain unchanged; active accesses may trap, and misaligned accesses may succeed or fault.
Pitfalls / Common Confusions
ei8 is the index EEW, not the SEW of the stored data; data element width still comes from current vtype.
vs2[i] is an unsigned byte offset; the address is x[rs1] + zero_extend(vs2[i]), not x[rs1] + i * EEW and not an element number.
The ordered indexed form writes elements in element order and obeys RVWMO at the element level; do not read it as a cache, pipeline, or bus implementation model.
With vm=0, elements disabled by v0.t perform no memory write and must not be shown as writing zero.