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VSOXEI64.V

RISC-V VSOXEI64.V Instruction Details

Instruction ManualV-type

Use x[rs1] plus the low XLEN bits of 64-bit vs2 indices as unsigned byte offsets for ordered indexed stores of active vs3 elements.

Instruction Syntax

vsoxei64.v vs3, (rs1), vs2, vm
Operand Breakdown
vs3: source vector register group providing active elements to store.
rs1: integer base-address register; unit-stride forms write consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector MemoryIndexed Vector Store
Related Search Terms
VSOXEI64.V instructionRISC-V VSOXEI64.Vvsoxei64.v syntaxvsoxei64.v encodingRVV indexed storeei64 indexordered indexed store

Instruction Behavior

VSOXEI64.V is a RISC-V V-extension ordered indexed vector store instruction. Each active element adds the address-width unsigned value of vs2[i] to x[rs1]: RV64 uses the full 64-bit index, while RV32 uses only its low 32 bits; it then stores the current-SEW data from vs3[i]. ei64 specifies only the index EEW. The ordered form observes stores in element order. With vm=0, elements disabled by v0.t do not write memory.

VSOXEI64.V Decode And Execute Animation

Decode the 64-bit indexed store, then compute each element address as x[rs1] + vs2[i].

Instruction input
vsoxei64.v
Execution context: index EEW=64, data SEW=32, index EEW and XLEN are both 64, so the full index value is used, ordered indexed accesses proceed in element order and obey RVWMO at the element level, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Encoding fieldsvsoxei64.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
11
25
vm
0
24..20
vs2
00100
19..15
rs1
01010
14..12
width
111
11..7
vd/vs3
01100
6..0
opcode
0100111
Address and data pathaddr[i] = 0x8000 + vs2[i]
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x0000000000000001
0x0000000000000004
0x0000000000000007
0x000000000000000a
0x000000000000000d
0x0000000000000010
0x0000000000000013
0x0000000000000016
0x0000000000000019
0x000000000000001c
0x000000000000001f
0x0000000000000022
0x0000000000000025
0x0000000000000028
0x000000000000002b
0x000000000000002e
addr
0x8001
0x8004
0x8007
0x800a
0x800d
0x8010
0x8013
0x8016
0x8019
0x801c
0x801f
0x8022
0x8025
0x8028
0x802b
0x802e
v12
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
...
...
-
...
...
...
...
-
...
...
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...
-
...
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Step 1 / 22

Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VSOXEI64.V is an RVV ordered indexed store: ei64 specifies index EEW, and RV32 address calculation uses only the low 32 bits of each 64-bit index. Memory writes occur only for active elements not masked off.

The ei64 in the mnemonic is the index EEW; index values are unsigned byte offsets, and RV32 address calculation uses only their low 32 bits.
Ordered indexed stores preserve observable element-store order.
vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VSOXEI64.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Ordered indirect writes

Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».

Device or side-effecting address spaces

Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».

Sparse table updates

Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is V-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

ei64 is the index EEW, not the SEW of the stored data; data element width still comes from current vtype.
vs2[i] supplies an unsigned byte offset: RV64 uses all 64 bits, while RV32 uses only the low 32 bits. The address is not x[rs1] + i * EEW and not an element number.
The ordered indexed form only states element-order observation; do not read it as a cache, pipeline, or bus implementation model.
With vm=0, elements disabled by v0.t perform no memory write and must not be shown as writing zero.

FAQ

What unit do VSOXEI64.V offsets or strides use?

Index values are unsigned byte offsets, not element numbers.