Is ei64 the data width for vsoxei64.v?
No. ei64 is the index EEW, meaning each index element in vs2 is 64 bits; the actual stored data width comes from current SEW.
VSOXEI64.V
RISC-V VSOXEI64.V Instruction Details
Instruction ManualV-typeRV64 V ordered indexed store: add 64-bit unsigned vs2 byte offsets to x[rs1] and store active SEW elements from vs3. RV32 V excludes ei64.
Instruction Syntax
vsoxei64.v vs3, (rs1), vs2, vm
Operand Breakdown
V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
Data EEW=SEW, EMUL=LMUL; index EMUL=(index EEW/SEW)*LMUL must be 1/8..8. Groups align; one register cannot provide different source EEWs, including EEW=1 v0. Inactive/tail make no access; vstart>=vl makes no access.
ei64 is supported by RV64 V; RV32 V excludes 64-bit indexes. Ordered stores obey RVWMO at element level. Sources remain unchanged; active accesses may trap, and misaligned accesses may succeed or fault.
VVector MemoryIndexed Vector Store
Instruction Behavior
VSOXEI64.V uses 64-bit unsigned byte offsets: address=x[rs1]+vs2[i], with current-SEW store data. Ordered accesses obey RVWMO in element order; masked-off elements make no access. V excludes 64-bit indexes when XLEN=32, so the general low-XLEN index rule does not provide RV32 V support.
VSOXEI64.V Decode And Execute Animation
Decode the 64-bit indexed store, then compute each element address as x[rs1] + vs2[i].
Instruction input
vsoxei64.v
Execution Context
Execution context: index EEW=64, data SEW=32, index EEW and XLEN are both 64, so the full index value is used, ordered indexed accesses proceed in element order and obey RVWMO at the element level, LMUL=m1, vstart=0 (a nonzero value starts at that element). These are not assembly syntax operands.
Teaching context: V 1.0, enabled vector state, valid supported vtype/SEW/index EEW; fix VLEN=4096, LMUL=m1, vstart=0, VLMAX=4096/32, index EMUL=2. Index groups align and stay within v31; a register cannot supply different source EEWs, and v0.t excludes v0 data sources. Equal-EEW vs3/vs2 sharing a register require equal elements. x0 gives base zero. Assume all active accesses succeed; misaligned accesses require environment support. The address display range 0..0xffffffff is a teaching limit, not an ISA limit. Rows show per-element store events, not a final byte-memory image; later overlapping stores may overwrite earlier data. Ordered stores obey RVWMO in element order. Stages are not processor cycles. Inactive/tail elements make no access; VL=0 makes no access. Sources remain unchanged; success resets vstart=0.
Encoding fieldsvsoxei64.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
11
25
vm
0
24..20
vs2
00100
19..15
rs1
01010
14..12
width
111
11..7
vd/vs3
01100
6..0
opcode
0100111
Address and data pathaddr[i] = 0x8000 + vs2[i]
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x0000000000000001
0x0000000000000004
0x0000000000000007
0x000000000000000a
0x000000000000000d
0x0000000000000010
0x0000000000000013
0x0000000000000016
0x0000000000000019
0x000000000000001c
0x000000000000001f
0x0000000000000022
0x0000000000000025
0x0000000000000028
0x000000000000002b
0x000000000000002e
addr
0x8001
0x8004
0x8007
0x800a
0x800d
0x8010
0x8013
0x8016
0x8019
0x801c
0x801f
0x8022
0x8025
0x8028
0x802b
0x802e
v12
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
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...
-
...
...
...
...
-
...
...
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-
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Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
RV64 V ordered indexed store: add 64-bit unsigned vs2 byte offsets to x[rs1] and store active SEW elements from vs3. RV32 V excludes ei64.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=11, width=111; the vs2 field names the index register.
Index EEW=64, EMUL=(64/SEW)*LMUL; data EEW=SEW, EMUL=LMUL. Indexes are byte offsets, without scaling by data width.
RV64 V only: V does not support 64-bit indexes when XLEN=32; RV64 uses the full unsigned 64-bit offset.
Ordered stores obey RVWMO in element order; later overlapping stores may overwrite earlier data. Source registers remain unchanged.
Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Inactive/tail elements make no access; VL=0 or vstart>=vl makes no access. Success resets vstart=0.
EMUL must be 1/8..8; groups align and stay within v31. A register cannot supply different source EEWs, including the EEW=1 v0.t mask. Unsupported index EEW is reserved. Accesses may trap; misaligned accesses may succeed or fault.
V 1.0 requires enabled vector state, vill=0 and supported vtype/SEW/LMUL; virtualization V=1 also requires non-Off vsstatus.VS.
Vector Execution Context
V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
Data EEW=SEW, EMUL=LMUL; index EMUL=(index EEW/SEW)*LMUL must be 1/8..8. Groups align; one register cannot provide different source EEWs, including EEW=1 v0. Inactive/tail make no access; vstart>=vl makes no access.
ei64 is supported by RV64 V; RV32 V excludes 64-bit indexes. Ordered stores obey RVWMO at element level. Sources remain unchanged; active accesses may trap, and misaligned accesses may succeed or fault.
Common Usage Scenarios
Ordered indirect writes
Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».
Device or side-effecting address spaces
Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».
Sparse table updates
Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».
Pre-Use Checklist
Syntax Check
- V 1.0 requires enabled vector state, vill=0 and supported vtype. Active elements have vstart<=i<vl and enabled mask; v0.t means vm=0, omission vm=1. Success resets vstart=0.
- Data EEW=SEW, EMUL=LMUL; index EMUL=(index EEW/SEW)*LMUL must be 1/8..8. Groups align; one register cannot provide different source EEWs, including EEW=1 v0. Inactive/tail make no access; vstart>=vl makes no access.
Semantic Check
- ei64 is supported by RV64 V; RV32 V excludes 64-bit indexes. Ordered stores obey RVWMO at element level. Sources remain unchanged; active accesses may trap, and misaligned accesses may succeed or fault.
Pitfalls / Common Confusions
ei64 is the index EEW, not the SEW of the stored data; data element width still comes from current vtype.
V does not support 64-bit indexes when XLEN=32; this is not a low-32-bit indexed store for RV32 V.
The ordered indexed form only states element-order observation; do not read it as a cache, pipeline, or bus implementation model.
With vm=0, elements disabled by v0.t perform no memory write and must not be shown as writing zero.
FAQ
Is vs2[i] an element index or an address offset?
On RV64 V it is a full unsigned 64-bit byte offset. RV32 V does not support ei64 indexes.
What does ordering mean for repeated addresses?
Stores obey RVWMO in element order. Address and data formulas are unchanged, but later stores to the same address may overwrite earlier data.