Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSOXEI64.V
RISC-V VSOXEI64.V Instruction Details
Instruction ManualV-typeUse x[rs1] plus 64-bit unsigned byte offsets from vs2 for ordered indexed stores from active vs3 elements.
Instruction Syntax
vsoxei64.v vs3, (rs1), vs2, vm
Operand Breakdown
vs3: source vector register group providing active elements to store.
rs1: integer base-address register; unit-stride forms write consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector MemoryIndexed Vector Store
Instruction Behavior
VSOXEI64.V is a RISC-V V-extension ordered indexed vector store instruction. Each active element forms its address as x[rs1] + zero_extend(vs2[i]) and stores the current-SEW data from vs3[i]; ei64 specifies only the index EEW. The ordered form observes stores in element order. With vm=0, elements disabled by v0.t do not write memory.
VSOXEI64.V Decode And Execute Animation
Decode the 64-bit indexed store, then compute each element address as x[rs1] + zero_extend(vs2[i]).
Instruction input
vsoxei64.v
Execution context: index EEW=64, data SEW=32, address=x[rs1]+zero_extend(vs2[i]), ordered indexed accesses are observed in element order, LMUL=m1. These are not assembly syntax operands.
Encoding fieldsvsoxei64.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
11
25
vm
0
24..20
vs2
00100
19..15
rs1
01010
14..12
width
111
11..7
vd/vs3
01100
6..0
opcode
0100111
Address and data pathaddr[i] = 0x8000 + vs2[i]
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
vs2 byte offset
0x0000000000000000
0x000000000000000c
0x0000000000000018
0x0000000000000018
0x0000000000000024
0x0000000000000030
0x0000000000000030
0x000000000000003c
0x0000000000000048
0x0000000000000048
0x0000000000000054
0x0000000000000060
0x0000000000000060
0x000000000000006c
0x0000000000000078
0x0000000000000078
addr
0x8000
0x800c
0x8018
0x8018
0x8024
0x8030
0x8030
0x803c
0x8048
0x8048
0x8054
0x8060
0x8060
0x806c
0x8078
0x8078
v12
0x00000101
0x00000202
0x00000303
0x00000404
0x00000505
0x00000606
0x00000707
0x00000808
0x00000909
0x00000a0a
0x00000b0b
0x00000c0c
0x00000d0d
0x00000e0e
0x00000f0f
0x00001010
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
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...
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...
...
...
...
-
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-
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Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VSOXEI64.V is an RVV ordered indexed store; memory writes occur only for active elements not masked off.
The ei64 in the mnemonic is the index EEW, and index values are unsigned byte offsets.
Ordered indexed stores preserve observable element-store order.
vm=0 uses v0 as the execution mask; masked-off elements do not perform memory writes.
Vector Execution Context
When reading VSOXEI64.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Ordered indirect writes
Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».
Device or side-effecting address spaces
Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».
Sparse table updates
Understand this scenario with real code like «vsoxei64.v v8, (a0), v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
ei64 is the index EEW, not the SEW of the stored data; data element width still comes from current vtype.
vs2[i] is an unsigned byte offset; the address is x[rs1] + zero_extend(vs2[i]), not x[rs1] + i * EEW and not an element number.
The ordered indexed form only states element-order observation; do not read it as a cache, pipeline, or bus implementation model.
With vm=0, elements disabled by v0.t perform no memory write and must not be shown as writing zero.
FAQ
What unit do VSOXEI64.V offsets or strides use?
Index values are unsigned byte offsets, not element numbers.