Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWSLL.VV
RISC-V VWSLL.VV Instruction Details
Instruction ManualV-type (OP-V / OPIVV)Zero-extend vs2 to 2*SEW; shift by vs1.
Instruction Syntax
vwsll.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
ZvbbVector Bit Manipulation
Instruction Behavior
Zero-extend vs2 to 2*SEW; shift by vs1 low log2(2*SEW) bits.
VWSLL.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWSLL zero-extends each SEW-wide vs2 element to 2*SEW, uses the low lg2(2*SEW) shift-count bits, and writes the widened logical-left-shift result.
Instruction input
vwsll.vv
Shift-count rule: only the low lg2(2*SEW) bits of the corresponding vs1 element are used.
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. The wide vd destination has EMUL=2 and must start at an even register; if it overlaps a SEW source, that source must be the highest-numbered register in the destination group. Such a legal different-EEW overlap is mask- and tail-agnostic regardless of vtype.vma/vta.In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingOPIVV vwsll.vv
funct6
110101
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
zext<<
zext<<
zext<<
zext<<
zext<<
zext<<
zext<<
zext<<
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwsll.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer widening logical left shift, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWSLL.VV is not ordinary VSLL; it zero-extends each SEW source element to 2*SEW and writes a widened destination group.
The widened output affects register-group size, overlap legality, and shift-amount bit selection.
vm is the ordinary V execution mask; masked-off elements follow V tail/mask policy.
Vector Execution Context
When reading VWSLL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vwsll.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vwsll.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type (OP-V / OPIVV).
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The destination element width is 2*SEW and must satisfy V widening EMUL/overlap constraints.
The source value is zero-extended first; do not describe this as signed widening.
The shift amount is truncated according to the 2*SEW result width.
FAQ
Does VWSLL.VV keep SEW width?
No. The destination element width is 2*SEW.
Is the source signed for VWSLL.VV?
The official description zero-extends before shifting, so do not treat it as signed widening.