Does VWSLL.VV keep SEW width?
No. The destination element width is 2*SEW.
VWSLL.VV
RISC-V VWSLL.VV Instruction Details
Instruction ManualR-typeVector widening logical left shift: zero-extend vs2 elements to 2*SEW, then shift left by a vector register amount.
Instruction Syntax
vwsll.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvbbVector Bit Manipulation
Instruction Behavior
VWSLL.VV is a Zvbb vector widening logical-left-shift instruction. Each active SEW element from vs2 is zero-extended to 2*SEW and shifted left by the vector register amount; only the low log2(2*SEW) bits are used.
Quick Understanding & Search Notes
VWSLL.VV is not ordinary VSLL; it zero-extends each SEW source element to 2*SEW and writes a widened destination group.
The widened output affects register-group size, overlap legality, and shift-amount bit selection.
vm is the ordinary V execution mask; masked-off elements follow V tail/mask policy.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vwsll.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vwsll.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The destination element width is 2*SEW and must satisfy V widening EMUL/overlap constraints.
The source value is zero-extended first; do not describe this as signed widening.
The shift amount is truncated according to the 2*SEW result width.
FAQ
Is the source signed for VWSLL.VV?
The official description zero-extends before shifting, so do not treat it as signed widening.