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VWSLL.VV

RISC-V VWSLL.VV Instruction Details

Instruction ManualR-type

Vector widening logical left shift: zero-extend vs2 elements to 2*SEW, then shift left by a vector register amount.

Instruction Syntax

vwsll.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
ZvbbVector Bit Manipulation
Related Search Terms
vwsll.vv instructionRISC-V vwsll.vvvwsll.vv syntaxvwsll.vv encodingvwsll.vv vector widening logical left shiftvwsll.vv 2*SEWvwsll.vv shift amount

Instruction Behavior

VWSLL.VV is a Zvbb vector widening logical-left-shift instruction. Each active SEW element from vs2 is zero-extended to 2*SEW and shifted left by the vector register amount; only the low log2(2*SEW) bits are used.

Quick Understanding & Search Notes

VWSLL.VV is not ordinary VSLL; it zero-extends each SEW source element to 2*SEW and writes a widened destination group.

The widened output affects register-group size, overlap legality, and shift-amount bit selection.
vm is the ordinary V execution mask; masked-off elements follow V tail/mask policy.
RISC-V Unprivileged ISA Manual: Vector Cryptography Extensions 1.0RISC-V Unprivileged ISA Manual: V standard vector extension

Vector Execution Context

When reading VWSLL.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vwsll.vv vd, vs2, vs1».

Vector Acceleration

Understand this scenario with real code like «vwsll.vv vd, vs2, vs1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The destination element width is 2*SEW and must satisfy V widening EMUL/overlap constraints.
The source value is zero-extended first; do not describe this as signed widening.
The shift amount is truncated according to the 2*SEW result width.

FAQ

Does VWSLL.VV keep SEW width?

No. The destination element width is 2*SEW.

Is the source signed for VWSLL.VV?

The official description zero-extends before shifting, so do not treat it as signed widening.