Does VWSLL.VV keep SEW width?
No. The destination element width is 2*SEW.
VWSLL.VV
RISC-V VWSLL.VV Instruction Details
Instruction ManualV-type (OP-V / OPIVV)Zero-extend vs2 to 2*SEW; shift by vs1.
Instruction Syntax
vwsll.vv vd, vs2, vs1[, v0.t]
Syntax: vwsll.vv vd, vs2, vs1[, v0.t]; vd/vs2/vs1 are vector registers and rs1 is an integer register. Equal sources require equal initial values.
32-bit OP-V: funct6=110101, funct3=000 (OPIVV), opcode=1010111. vm=0 uses v0.t; omitting it gives vm=1.
Zvbb depends on Zve32x; require SEW and 2*SEW support. Zero-extend vs2 to 2*SEW, shift by the low log2(2*SEW) count bits and keep low 2*SEW bits. This is neither signed widening nor rotation.
Destination EMUL=2*LMUL≤8; groups follow EMUL alignment. A narrow source with EMUL≥1 may overlap only the highest end of vd, forcing ma/ta. With vm=0, destination excludes v0; data sources cannot also use the EEW=1 mask v0.
Require enabled vector state and valid vtype. Process active body only; preserve prestart and follow vma/vta for inactive/tail. vstart≥vl (including vl=0) updates nothing; success clears vstart. SEW=64 widening needs additional 128-bit integer elements.
ZvbbVector Bit Manipulation
Instruction Behavior
Zero-extend vs2 to 2*SEW; shift by vs1 low log2(2*SEW) bits.
VWSLL.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWSLL zero-extends each SEW-wide vs2 element to 2*SEW, uses the low lg2(2*SEW) shift-count bits, and writes the widened logical-left-shift result.
Instruction input
vwsll.vv
Teaching context: Zvbb, enabled vector state, valid supported vtype, and support for SEW and 2*SEW; SEW=64 needs additional 128-bit integer elements. Fix LMUL=m1, VLEN=4096, vstart=0. Inputs are nonnegative SEW bit patterns; zero-extend to 2*SEW, shift by the low log2(2*SEW) count bits and retain low 2*SEW bits. .vi uimm is 0–31; .vx x0 supplies zero. vd is an even-start EMUL=2 group; narrow overlap is allowed only at its highest register and forces ma/ta. With v0.t, destination and data sources exclude v0. Equal sources require equal initial values. Show body only without definite inactive/tail values; VL=0 updates nothing. Stages are not processor cycles.
Execution Context
Shift-count rule: only the low lg2(2*SEW) bits of the corresponding vs1 element are used.
OP-V encodingOPIVV vwsll.vv
funct6
110101
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
zext<<
zext<<
zext<<
zext<<
zext<<
zext<<
zext<<
zext<<
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwsll.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer widening logical left shift, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
Zero-extend each SEW source, then shift into a 2*SEW destination group.
Zvbb depends on Zve32x. Both source SEW and destination 2*SEW must be supported, with EMUL=2*LMUL≤8. Widening SEW=64 needs additional 128-bit integer element support beyond baseline V guarantees.
32-bit OP-V: funct6=110101, funct3=000 (OPIVV), opcode=1010111; The second source supplies the shift count.
Zero-extend each active vs2 element to 2*SEW, shift by the low log2(2*SEW) count bits and keep low 2*SEW bits. Groups follow EMUL alignment; a narrower source may overlap only the destination’s highest end with source EMUL≥1, forcing mask/tail-agnostic behavior.
Omit v0.t for vm=1; include it for vm=0. A masked destination excludes v0, which cannot supply both mask and SEW data. Equal sources read equal values.
Require enabled vector state and valid vtype. Execute only active body elements; preserve prestart and follow vma/vta for inactive/tail. vstart≥vl (including vl=0) updates no destination; success clears vstart.
Vector Execution Context
Syntax: vwsll.vv vd, vs2, vs1[, v0.t]; vd/vs2/vs1 are vector registers and rs1 is an integer register. Equal sources require equal initial values.
32-bit OP-V: funct6=110101, funct3=000 (OPIVV), opcode=1010111. vm=0 uses v0.t; omitting it gives vm=1.
Zvbb depends on Zve32x; require SEW and 2*SEW support. Zero-extend vs2 to 2*SEW, shift by the low log2(2*SEW) count bits and keep low 2*SEW bits. This is neither signed widening nor rotation.
Destination EMUL=2*LMUL≤8; groups follow EMUL alignment. A narrow source with EMUL≥1 may overlap only the highest end of vd, forcing ma/ta. With vm=0, destination excludes v0; data sources cannot also use the EEW=1 mask v0.
Require enabled vector state and valid vtype. Process active body only; preserve prestart and follow vma/vta for inactive/tail. vstart≥vl (including vl=0) updates nothing; success clears vstart. SEW=64 widening needs additional 128-bit integer elements.
Common Usage Scenarios
Widening logical shift
vwsll.vv v4, v8, v12 # SEW=16, LMUL=1; vs2[0]=0x8000, shift=3 => vd[0]=0x00040000. Initialize the stated source values and enable the listed extension and relevant state; the comment gives the result derived from this page's rules.
Zero-extension bit operations
vwsll.vv v4, v8, v12 # SEW=16, LMUL=1; vs2[0]=0x8000, shift=3 => vd[0]=0x00040000. Initialize the stated source values and enable the listed extension and relevant state; the comment gives the result derived from this page's rules.
Pre-Use Checklist
Syntax Check
- Syntax: vwsll.vv vd, vs2, vs1[, v0.t]; vd/vs2/vs1 are vector registers and rs1 is an integer register. Equal sources require equal initial values.
- 32-bit OP-V: funct6=110101, funct3=000 (OPIVV), opcode=1010111. vm=0 uses v0.t; omitting it gives vm=1.
Semantic Check
- Zvbb depends on Zve32x; require SEW and 2*SEW support. Zero-extend vs2 to 2*SEW, shift by the low log2(2*SEW) count bits and keep low 2*SEW bits. This is neither signed widening nor rotation.
- Destination EMUL=2*LMUL≤8; groups follow EMUL alignment. A narrow source with EMUL≥1 may overlap only the highest end of vd, forcing ma/ta. With vm=0, destination excludes v0; data sources cannot also use the EEW=1 mask v0.
- Require enabled vector state and valid vtype. Process active body only; preserve prestart and follow vma/vta for inactive/tail. vstart≥vl (including vl=0) updates nothing; success clears vstart. SEW=64 widening needs additional 128-bit integer elements.
Pitfalls / Common Confusions
The destination element width is 2*SEW and must satisfy V widening EMUL/overlap constraints.
The source value is zero-extended first; do not describe this as signed widening.
The shift amount is truncated according to the 2*SEW result width.
FAQ
Is the source signed for VWSLL.VV?
The official description zero-extends before shifting, so do not treat it as signed widening.