ble

RISC-V ble Pseudo-Instruction Details

Assembler pseudo-instruction

Signed less-or-equal branch pseudo-instruction. It swaps source registers and uses BGE: ble rs1, rs2, offset is equivalent to bge rs2, rs1, offset.

What You Write

ble rs1, rs2, offset

Typical Real Expansion

bge rs2, rs1, offset

What This Pseudo Instruction Is Saving You From Writing

Base RISC-V branches provide a compact set such as equal/not-equal and less-than/greater-or-equal; this pseudo-instruction swaps operands or compares with x0 so source code matches the programmer condition.

ble primarily means "Signed less-or-equal branch". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats ble as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of BGE and the other expanded instructions, not from a separate ble hardware opcode.

Signed or unsigned comparison behavior is inherited from BEQ/BNE/BLT/BGE/BLTU/BGEU; zero-test aliases simply use x0 as one operand.

How To Read The Expansion

Step 1

Assembler expands to bge rs2, rs1, offset

What You May See In objdump / Disassembly

Disassemblers may show the pseudo name or the expanded real branch; when reading semantics, check whether rs1/rs2 were swapped.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Lower bound checks

Loop termination tests

Signed value range checks

Pitfalls / Common Confusions

This is a signed comparison; do not use it for addresses or unsigned sizes

Branch target range comes from the real B-type branch immediate, about ±4 KiB

Some forms are implemented by swapping operands; do not reverse the operands incorrectly when expanding by hand

FAQ

Is ble a real RISC-V instruction?

ble is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using ble?