RISC-V j Pseudo-Instruction Details

Assembler pseudo-instruction

Unconditional jump pseudo-instruction expands to jal x0, offset. Transfers control within ±1 MiB without saving a return address. Commonly used for goto, infinite loops, and switch-case jump tables.

What You Write

j offset

Typical Real Expansion

jal x0, offset

What This Pseudo Instruction Is Saving You From Writing

More readable than jal x0, offset; explicitly conveys 'jump without returning.' Contrasts with call — j does not save ra, suitable for no-return control transfers.

j primarily means "Unconditional jump, no return address". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats j as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of JAL and the other expanded instructions, not from a separate j hardware opcode.

Toolchain And Linker Boundaries

j is the assembler alias for jal x0, offset; if the target is outside the JAL immediate range, the toolchain or source must use another far-jump sequence.

A disassembler may show j or the real JAL form; reason from rd=x0 and JAL semantics.

How To Read The Expansion

Step 1

Assembler expands j offset to jal x0, offset.

Step 2

JAL computes PC+offset as the target, simultaneously writes PC+4 to x0 (discarded by hardware), completing only the jump.

What You May See In objdump / Disassembly

jal x0, offset shown as j offset in disassembly. Note the difference from call — call writes ra and may be relaxed; j always writes x0.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Implement goto / break / continue control flow

Infinite loop back-edges (while-true tail jump)

Switch-case jump table entries

Unconditional control transfer (no return needed)

Pitfalls / Common Confusions

Range limited to ±1 MiB (JAL J-type immediate range); use a farther jump sequence for longer distances

Does not push the return address stack (RAS) predictor, unlike call — CPU branch predictor handles this differently

j writes x0=0 as rd, so the next-instruction address is saved nowhere

FAQ

Is j a real RISC-V instruction?

j is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using j?