mv
RISC-V mv Pseudo-Instruction Details
Assembler pseudo-instructionRISC-V mv is written as mv rd, rs in the RISC-V Assembly Programmer's Manual and expands to addi rd, rs, 0. The Unprivileged ISA states that ADDI rd, rs1, 0 implements MV.
What You Write
mv rd, rs
Typical Real Expansion
addi rd, rs, 0
What This Pseudo Instruction Is Saving You From Writing
mv expresses a register copy as addi rd, rs, 0.
How To Read The Expansion
Step 1
The assembler writes mv rd, rs as addi rd, rs, 0.
Step 2
ADDI writes the low XLEN result of rs plus its sign-extended 12-bit immediate to rd; here the immediate is zero.
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
Pitfalls / Common Confusions
The actual behavior is defined by ADDI, not by a separate mv hardware opcode.
FAQ
Is mv a separate hardware opcode?
No. mv is an assembler pseudo-instruction for addi rd, rs, 0.