not

RISC-V not Pseudo-Instruction Details

Assembler pseudo-instruction

Bitwise NOT pseudo-instruction, expands to xori rd, rs, -1. Flips every bit of register rs (0→1, 1→0) and stores in rd. Common for bitmask generation, bit clearing, and logic operations.

What You Write

not rd, rs

Typical Real Expansion

xori rd, rs, -1

What This Pseudo Instruction Is Saving You From Writing

More natural than xori rd, rs, -1. Exploits XOR with all-ones property — any bit XOR 1 flips — to concisely implement NOT.

not primarily means "Bitwise complement of all bits". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats not as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of XORI and the other expanded instructions, not from a separate not hardware opcode.

How To Read The Expansion

Step 1

Assembler expands to xori rd, rs, -1.

Step 2

-1 encodes as 0xFFF in 12 bits, sign-extended to 64-bit all-ones (0xFFFFFFFFFFFFFFFF).

Step 3

XORI XORs each bit of rs with 1, achieving bitwise inversion.

What You May See In objdump / Disassembly

xori rd, rs, -1 shown as not rd, rs in disassembly. -1 equals 0xFFF in the 12-bit signed immediate.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

When To Think Of It First

Generate complement of a bitmask (mask & ~bits)

Implement C bitwise NOT operator ~

Clear specific bits in a register

Compute ~0 (all-ones) with not rd, zero

Pitfalls / Common Confusions

NOT acts on the whole register width (RV32=32 bits, RV64=64 bits), so match it to the intended data width

The -1 immediate of XORI is sign-extended from 12 bits to all ones, which is why this pseudo-instruction works

not produces a full bitwise complement; to flip only selected low bits, build a mask and use xor instead

FAQ

Is not a real RISC-V instruction?

not is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using not?