RISC-V snez Pseudo-Instruction Details
Assembler pseudo-instructionRISC-V snez pseudo-instruction expands to sltu rd, x0, rs. SLTU is an unsigned comparison; this form writes 1 to rd only when rs is not zero, otherwise 0.
What This Pseudo Instruction Is Saving You From Writing
Directly expresses a nonzero test: SLTU uses unsigned comparison, so 0 < rs if and only if rs != 0. The result is 1 when rs is nonzero and 0 otherwise.
Official Semantics Checklist
How To Read The Expansion
Assembly Forms And Real Instructions
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
When To Think Of It First
Pitfalls / Common Confusions
FAQ
Is snez a real RISC-V instruction?
snez is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.
What is the main trap when using snez?
SNEZ is unsigned-based — but 0 < rs (unsigned) iff rs != 0, semantically correct in all cases