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snez

RISC-V snez Pseudo-Instruction Details

Assembler pseudo-instruction

Set if not equal zero pseudo-instruction, expands to sltu rd, x0, rs. Sets rd=1 if rs!=0, else rd=0. rd = (rs != 0) ? 1 : 0. Equivalent to unsigned comparison rs > 0.

What You Write
snez rd, rs
Typical Real Expansion
sltu rd, x0, rs

What This Pseudo Instruction Is Saving You From Writing

Booleanize non-zero values. Exploits SLTU semantics: 0 < rs (unsigned) iff rs != 0. The result is consistent with C bool conversion (non-zero → true → 1).

snez primarily means "Set 1 if not equal to zero". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats snez as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.
The real semantics come from the ISA definitions of SLTU and the other expanded instructions, not from a separate snez hardware opcode.

How To Read The Expansion

Step 1
Assembler expands to sltu rd, x0, rs.
Step 2
SLTU performs unsigned comparison: if x0(0) < rs (i.e., rs != 0), rd = 1; else rd = 0.

What You May See In objdump / Disassembly

sltu rd, x0, rs shown as snez rd, rs in disassembly. x0 provides constant 0 as the source operand.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

When To Think Of It First

Booleanize any value (C bool conversion: non-zero → true)
Detect non-zero computation results or return values
Build conditional masks (mark non-zero elements)
Pointer existence verification

Pitfalls / Common Confusions

SNEZ is unsigned-based — but 0 < rs (unsigned) iff rs != 0, semantically correct in all cases
snez's semantics are consistent with C bool conversion (non-zero → 1), opposite to seqz
On RV64, if the low 32 bits of rs are zero but the high 32 bits are non-zero, snez still returns 1 (the full 64-bit value participates in unsigned comparison)

FAQ

Is snez a real RISC-V instruction?

snez is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using snez?

SNEZ is unsigned-based — but 0 < rs (unsigned) iff rs != 0, semantically correct in all cases