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bnez

RISC-V bnez Pseudo-Instruction Details

Assembler pseudo-instruction

Branch if not equal zero pseudo-instruction, expands to bne rs, x0, offset. Branches when a register is non-zero. Common for non-null guard checks, loop continuation, and boolean testing.

What You Write
bnez rs, offset
Typical Real Expansion
bne rs, x0, offset

What This Pseudo Instruction Is Saving You From Writing

More naturally expresses 'if non-zero, branch' control flow than bne rs, x0, offset. Complements beqz, together covering all zero/non-zero branch needs.

bnez primarily means "Branch if register not zero". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats bnez as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.
The real semantics come from the ISA definitions of BNE and the other expanded instructions, not from a separate bnez hardware opcode.
Signed or unsigned comparison behavior is inherited from BEQ/BNE/BLT/BGE/BLTU/BGEU; zero-test aliases simply use x0 as one operand.

How To Read The Expansion

Step 1
Assembler expands to bne rs, x0, offset.
Step 2
BNE compares rs with x0 (always 0); if not equal, PC ← PC + offset × 2.

What You May See In objdump / Disassembly

bne rs, x0, offset shown as bnez rs, offset in disassembly.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual
RISC-V Unprivileged ISA Manual

When To Think Of It First

Check result is non-zero before use (guard pattern)
Continue execution after non-null pointer check
Loop count check (continue if current iteration not done)
Boolean testing (if (flag) branch)

Pitfalls / Common Confusions

±4 KiB branch range limit — far branches need bnez + j combo
BNEZ does not check sign; do not confuse with BGEZ (≥0) — BNEZ only checks for non-zero
On RV64, BNEZ checks the full 64-bit value — it still branches if the low 32 bits are zero but the high 32 bits are not

FAQ

Is bnez a real RISC-V instruction?

bnez is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using bnez?

±4 KiB branch range limit — far branches need bnez + j combo