beqz

RISC-V beqz Pseudo-Instruction Details

Assembler pseudo-instruction

Branch if equal zero pseudo-instruction, expands to beq rs, x0, offset. Branches when a register equals zero. Common for null pointer checks, loop termination, and flag testing.

What You Write

beqz rs, offset

Typical Real Expansion

beq rs, x0, offset

What This Pseudo Instruction Is Saving You From Writing

More naturally expresses 'branch if zero' control flow than beq rs, x0, offset. The assembler provides it as an alias to simplify code reading and writing.

beqz primarily means "Branch if register equals zero". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats beqz as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of BEQ and the other expanded instructions, not from a separate beqz hardware opcode.

Signed or unsigned comparison behavior is inherited from BEQ/BNE/BLT/BGE/BLTU/BGEU; zero-test aliases simply use x0 as one operand.

How To Read The Expansion

Step 1

Assembler expands to beq rs, x0, offset.

Step 2

BEQ compares rs with x0 (always 0); if equal, PC ← PC + offset × 2.

What You May See In objdump / Disassembly

beq rs, x0, offset shown as beqz rs, offset in disassembly.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Null pointer checks (ptr == NULL)

Loop termination (exit when counter reaches zero)

malloc/realloc return value validation

Resource release branch when reference count drops to zero

Pitfalls / Common Confusions

Branch range is only ±4 KiB (B-type immediate limit) — far branches need beqz + j combo

beqz checks if the entire register (XLEN) equals zero, not just the lower 32 bits

It is only an assembler alias; debug machine code as beq rs, x0, offset

FAQ

Is beqz a real RISC-V instruction?

beqz is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using beqz?