This workbench follows the official RISC-V assembly manual for pseudo-instructions, assembler aliases, and standard encoding spellings, so you can read li, call, ret, fence.tso, and related forms before checking the real instruction or encoding for behavior, range, and caveats.
Pseudo-instructions and assembly forms belong to the assembler layer; performance, traps, extension requirements, and immediate ranges come from the expanded real instruction or encoding.
The same spelling may vary by XLEN, PIC/nopic mode, symbol distance, available extensions, or linker relaxation; detail pages call out the common paths.
Expansion tables follow the RISC-V Assembly Programmer's Manual; real-instruction semantics follow the Unprivileged ISA; ABI and relocation wording follows the psABI.
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Far function call pseudo-instruction using an AUIPC+JALR PC-relative call sequence. Unlike JAL's ±1 MiB limit, call is common for cross-module, shared-library, or dynamically linked calls and can be relaxed by the linker.
Unconditional jump pseudo-instruction expands to jal x0, offset. Transfers control within ±1 MiB without saving a return address. Commonly used for goto, infinite loops, and switch-case jump tables.
Load-integer-immediate pseudo-instruction. The assembler chooses one or more real instructions according to the constant, XLEN, and available extensions; small signed 12-bit values can use ADDI, while larger constants commonly need LUI/ADDI or more steps.
Register-to-register copy pseudo-instruction, expands to addi rd, rs, 0. Expresses assignment semantics more clearly than raw ADDI. Heavily used by compilers for register allocation, function argument setup, and temporary value preservation.
No-operation pseudo-instruction, expands to addi x0, x0, 0. Changes no architectural state except advancing PC. Primarily used for code alignment, icache line padding, and runtime code patch reservation.
Return from subroutine pseudo-instruction, expands to jalr x0, 0(ra). Jumps back to the caller indirectly via the ra register. The standard return mechanism in RISC-V function epilogues.
Load-address pseudo-instruction that places a symbol address in a register. The official assembly manual defines different expansions for .option nopic versus pic: typically AUIPC+ADDI for non-PIC and GOT-indirect loading for PIC.
Branch if equal zero pseudo-instruction, expands to beq rs, x0, offset. Branches when a register equals zero. Common for null pointer checks, loop termination, and flag testing.
Branch if not equal zero pseudo-instruction, expands to bne rs, x0, offset. Branches when a register is non-zero. Common for non-null guard checks, loop continuation, and boolean testing.
Register-indirect jump pseudo-instruction, commonly expanded as jalr x0, 0(rs). It does not save a return address; it only transfers control to the target address held in a register.
Tail call pseudo-instruction, expands to AUIPC t1 + JALR x0 (no return address saved). It is used when the final action of a function jumps to another function, whose return goes directly to the current function's caller.
Negate (two's complement) pseudo-instruction, expands to sub rd, x0, rs. Computes 0 - rs to obtain the arithmetic negation of rs. Common for sign flipping, absolute value pre-computation, and subtraction optimization.
Bitwise NOT pseudo-instruction, expands to xori rd, rs, -1. Flips every bit of register rs (0→1, 1→0) and stores in rd. Common for bitmask generation, bit clearing, and logic operations.
Set if equal zero pseudo-instruction, expands to sltiu rd, rs, 1. Sets rd=1 if rs==0, else rd=0. rd = (rs == 0) ? 1 : 0. Common for null pointer checks and booleanization.
Set if not equal zero pseudo-instruction, expands to sltu rd, x0, rs. Sets rd=1 if rs!=0, else rd=0. rd = (rs != 0) ? 1 : 0. Equivalent to unsigned comparison rs > 0.
Load-global-address pseudo-instruction that obtains a global symbol address through a GOT PC-relative sequence. The official assembly manual gives AUIPC plus LW on RV32 or LD on RV64 as the base form.
Load-local-address pseudo-instruction that expands, per the official assembly manual, to a PC-relative AUIPC+ADDI sequence. It fits local symbols or non-PIC address paths that do not need GOT indirection.
Set-if-greater-than-zero pseudo-instruction, expanding to slt rd, x0, rs. If rs is greater than 0 as a signed value, rd=1; otherwise rd=0.
Set-if-less-than-zero pseudo-instruction, expanding to slt rd, rs, x0. If rs is less than 0 as a signed value, rd=1; otherwise rd=0.
Read-CSR pseudo-instruction, expanding to csrrs rd, csr, x0. It reads the selected CSR into rd and requests no bit set because rs1=x0.
Write-CSR pseudo-instruction, expanding to csrrw x0, csr, rs. It writes rs to the CSR and does not read or return the old CSR value because rd=x0.
Clear-CSR-bits pseudo-instruction, expanding to csrrc x0, csr, rs. It atomically clears CSR bits selected by 1 bits in rs and does not return the old value.
Set-CSR-bits pseudo-instruction, expanding to csrrs x0, csr, rs. It atomically sets CSR bits selected by 1 bits in rs and does not return the old value.
Immediate clear-CSR-bits pseudo-instruction, expanding to csrrci x0, csr, uimm. It clears CSR bits selected by 1 bits in the 5-bit immediate and does not return the old value.
Immediate set-CSR-bits pseudo-instruction, expanding to csrrsi x0, csr, uimm. It sets CSR bits selected by 1 bits in the 5-bit immediate and does not return the old value.
Immediate write-CSR pseudo-instruction, expanding to csrrwi x0, csr, uimm. It writes the 5-bit unsigned immediate to the CSR and does not return the old value.
Branch-if-greater-or-equal-zero pseudo-instruction, expanding to bge rs, x0, offset. It uses a signed comparison to test whether a register is non-negative, common in sign checks, loop bounds, and error-code tests.
Signed greater-than branch pseudo-instruction. It swaps the two source registers and uses BLT: bgt rs1, rs2, offset is equivalent to blt rs2, rs1, offset.
Unsigned greater-than branch pseudo-instruction. It swaps the two source registers and uses BLTU: bgtu rs1, rs2, offset is equivalent to bltu rs2, rs1, offset.
Branch-if-greater-than-zero pseudo-instruction, expanding to blt x0, rs, offset. It uses a signed comparison to test whether rs is strictly greater than 0.
Signed less-or-equal branch pseudo-instruction. It swaps source registers and uses BGE: ble rs1, rs2, offset is equivalent to bge rs2, rs1, offset.
Unsigned less-or-equal branch pseudo-instruction. It swaps source registers and uses BGEU: bleu rs1, rs2, offset is equivalent to bgeu rs2, rs1, offset.
Branch-if-less-or-equal-zero pseudo-instruction, expanding to bge x0, rs, offset. It uses a signed comparison to test whether rs is not greater than 0.
Branch-if-less-than-zero pseudo-instruction, expanding to blt rs, x0, offset. It uses a signed comparison to test whether the register is negative.
Read-fflags pseudo-instruction, expanding to csrrs rd, fflags, x0. fflags holds accrued floating-point exception flags.
Write-fflags pseudo-instruction. The common read/write form expands to csrrw rd, fflags, rs; an x0 form does not return old exception flags.
Read-fcsr pseudo-instruction, expanding to csrrs rd, fcsr, x0. fcsr combines the floating-point rounding mode frm and exception flags fflags.
Read-frm pseudo-instruction, expanding to csrrs rd, frm, x0. frm holds the dynamic floating-point rounding-mode encoding.
Write-fcsr pseudo-instruction. The common read/write form expands to csrrw rd, fcsr, rs and returns the old value in rd; an x0 form does not return the old value.
Immediate write-fflags pseudo-instruction, expanding to csrrwi rd, fflags, uimm or an x0 form that does not return the old value. It directly writes the floating-point exception flag field.
Write-frm pseudo-instruction. The common read/write form expands to csrrw rd, frm, rs; an x0 form does not return the old rounding mode.
Immediate write-frm pseudo-instruction, expanding to csrrwi rd, frm, uimm or an x0 form that does not return the old value. uimm is the 5-bit CSR immediate field.
Omitted-rd form of JAL, expanding to jal ra, offset. It saves the return address in ra for near direct calls within the ±1 MiB JAL range.
Omitted-operand forms of JALR, commonly defaulting to ra as the link register and offset 0. It is used for indirect calls through a target address held in a register.
RV64 sign-extend-word pseudo-instruction, expanding to addiw rd, rs, 0. It takes the low 32 bits of rs and sign-extends bit 31 to XLEN.
RV64 word-negate pseudo-instruction, expanding to subw rd, x0, rs. It negates only the low 32 bits in two’s-complement arithmetic and sign-extends the 32-bit result to XLEN.
Read-cycle-counter pseudo-instruction, expanding to csrrs rd, cycle, x0. It reads the low XLEN bits of the processor cycle counter.
Read-cycleh-counter pseudo-instruction, expanding to csrrs rd, cycleh, x0. On RV32 it reads the high 32 bits of cycle; RV64 generally does not use the h-suffixed form.
Read-instret-counter pseudo-instruction, expanding to csrrs rd, instret, x0. It reads the low XLEN bits of the retired-instruction counter.
Read-instreth-counter pseudo-instruction, expanding to csrrs rd, instreth, x0. On RV32 it reads the high 32 bits of instret; RV64 generally does not use the h-suffixed form.
Read-time-counter pseudo-instruction, expanding to csrrs rd, time, x0. It reads the low XLEN bits of the platform-provided real-time counter.
Read-timeh-counter pseudo-instruction, expanding to csrrs rd, timeh, x0. On RV32 it reads the high 32 bits of time; RV64 generally does not use the h-suffixed form.
Zero-extend-byte pseudo-instruction, expressible per the official assembly manual as andi rd, rs, 255. It keeps the low 8 bits and clears the high bits.
Zero-extend-halfword pseudo-instruction that keeps the low 16 bits and clears the high bits. Without Zbb it can use a shift-left/logical-shift-right sequence; with Zbb it can use a single instruction form.
RV64 zero-extend-word pseudo-instruction that keeps the low 32 bits and clears the high bits. Without Zba it can use an slli/srli sequence; with Zba it can use add.uw.
PAUSE hint pseudo-instruction, listed in the official assembly manual as fence w, 0. It is used in spin-wait loops to give implementations an opportunity to reduce resource contention or power.
Older breakpoint pseudo-instruction name, expanding to ebreak. It preserves compatibility with earlier assembly spelling; modern code typically writes EBREAK directly.
Older system-call pseudo-instruction name, expanding to ecall. It preserves compatibility with earlier assembly spelling; modern code typically writes ECALL directly.
fence.tso is a TSO memory-ordering spelling encoded as the FENCE TSO/fm=1000, pred=rw, succ=rw form. It expresses TSO-style ordering and is not merely the ordinary textual form fence rw,rw.