rdinstret

RISC-V rdinstret Pseudo-Instruction Details

Assembler pseudo-instruction

RISC-V rdinstret is the pseudo-instruction for the instret CSR and expands to csrrs rd, instret, x0. It reads the low XLEN bits; instret counts instructions retired by this hart from an arbitrary past start point.

What You Write

rdinstret rd

Typical Real Expansion

csrrs rd, instret, x0

What This Pseudo Instruction Is Saving You From Writing

The assembly manual lists rdinstret as the standard counter-read spelling for csrrs rd, instret, x0.

rdinstret reads the low XLEN bits of instret.

Availability And Extension Conditions

Base Conditions

Zicntr depends on Zicsr
Reads the low XLEN bits of instret

Single-Instruction Or Standard Form

The execution environment permits counter access

Fallback / Boundary

Some execution environments may prohibit counter access; an RV32 full instret value needs the rdinstreth high-half read.

Notes

Instructions causing synchronous exceptions, including ECALL and EBREAK, do not retire or increment instret.

How To Read The Expansion

Step 1

CSRRS with rs1=x0 reads the read-only instret CSR; this canonical form does not write the CSR.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 30 Table 6

RISC-V Unprivileged ISA Manual 2026-01-20, Section 7.1

When To Think Of It First

Read the count of instructions retired by this hart

Pitfalls / Common Confusions

Zicntr depends on Zicsr, and some execution environments may prohibit counter access.

When XLEN=32, rdinstret reads only the low 32 bits; a full value needs the rdinstreth high-half read.

Instructions causing synchronous exceptions, including ECALL and EBREAK, do not retire and do not increment instret.

FAQ

Is rdinstret a real RISC-V instruction?

rdinstret is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using rdinstret?

Synchronously excepting instructions do not retire or increment instret; an RV32 full value needs the rdinstreth high-half read.