rdcycle

RISC-V rdcycle Pseudo-Instruction Details

Assembler pseudo-instruction

RISC-V rdcycle is the pseudo-instruction for the cycle CSR and expands to csrrs rd, cycle, x0. It reads the low XLEN bits; when XLEN is at least 64, it reads the full 64-bit counter.

What You Write

rdcycle rd

Typical Real Expansion

csrrs rd, cycle, x0

What This Pseudo Instruction Is Saving You From Writing

The assembly manual lists rdcycle as the standard counter-read spelling for csrrs rd, cycle, x0.

rdcycle reads the low XLEN bits of cycle.

Availability And Extension Conditions

Base Conditions

Zicntr depends on Zicsr
Reads the low XLEN bits of cycle

Single-Instruction Or Standard Form

The execution environment permits counter access

Fallback / Boundary

Some execution environments may prohibit counter access; RV32 full reads use a high-low-high comparison retry.

Notes

The cycle rate depends on the implementation and execution environment.

How To Read The Expansion

Step 1

CSRRS with rs1=x0 reads the read-only cycle CSR; this canonical form does not write the CSR.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 30 Table 6

RISC-V Unprivileged ISA Manual 2026-01-20, Section 7.1

When To Think Of It First

Read processor-core clock cycles for the ISA's performance-monitoring use

Pitfalls / Common Confusions

Zicntr depends on Zicsr, and some execution environments may prohibit counter access.

When XLEN=32, rdcycle reads only the low 32 bits; use the manual's high-low-high comparison retry sequence for a full cycle value.

cycle counts processor-core clock cycles from an arbitrary past start time; its rate depends on the implementation and execution environment.

FAQ

Is rdcycle a real RISC-V instruction?

rdcycle is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using rdcycle?

On RV32, rdcycle reads only the low 32 bits; a high-low-high comparison retry obtains a valid full cycle value.