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rdcycleh

RISC-V rdcycleh Pseudo-Instruction Details

Assembler pseudo-instruction

Read-cycleh-counter pseudo-instruction, expanding to csrrs rd, cycleh, x0. On RV32 it reads the high 32 bits of cycle; RV64 generally does not use the h-suffixed form.

What You Write
rdcycleh rd
Typical Real Expansion
csrrs rd, cycleh, x0

What This Pseudo Instruction Is Saving You From Writing

Counters are read-only CSRs; the pseudo-instruction hides the fixed CSRRS rd, csr, x0 form and makes performance/time reads clearer.

rdcycleh primarily means "Read RV32 high counter half". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats rdcycleh as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.
The real semantics come from the ISA definitions of CSRRS and the other expanded instructions, not from a separate rdcycleh hardware opcode.
CSR read, write, set, clear, and immediate behavior follows the Zicsr CSRRW/CSRRS/CSRRC instructions and their immediate variants.

Availability And Extension Conditions

Base Conditions
  • RV32 high-half counter read
Single-Instruction Or Standard Form
  • The cycleh CSR access form exists on RV32
Fallback / Boundary
RV64 normally reads the XLEN-wide cycle value directly and does not use the h-suffixed form.
Notes
  • Whether lower privilege levels can read counters depends on platform and CSR access control.

How To Read The Expansion

Step 1
CSRRS reads the high half of the cycle counter on RV32; rs1=x0 leaves the counter unchanged.

What You May See In objdump / Disassembly

Disassembly may show rdcycle/rdtime/rdinstret or csrrs rd, csr, x0.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual
RISC-V Unprivileged ISA Manual

When To Think Of It First

Measure cycles or retired instructions for a short code region
Read a platform time base
Write benchmarks, runtime-library code, or low-level diagnostics

Pitfalls / Common Confusions

The h-suffixed form is mainly for RV32 reads of the high half of a 64-bit counter
Whether lower privilege levels can read the counters depends on platform and CSR access control
In multicore or dynamic-frequency environments, cycle/time interpretation is platform-defined

FAQ

Is rdcycleh a real RISC-V instruction?

rdcycleh is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using rdcycleh?

The h-suffixed form is mainly for RV32 reads of the high half of a 64-bit counter