rdcycleh

RISC-V rdcycleh Pseudo-Instruction Details

Assembler pseudo-instruction

RISC-V rdcycleh is the pseudo-instruction for the cycle high half and expands to csrrs rd, cycleh, x0. It exists only when XLEN=32 and reads bits 63 through 32 of the same 64-bit cycle counter.

What You Write

rdcycleh rd

Typical Real Expansion

csrrs rd, cycleh, x0

What This Pseudo Instruction Is Saving You From Writing

The assembly manual's rdcycle[h] row lists the standard counter-read spelling csrrs rd, cycle[h], x0.

rdcycleh reads cycle bits 63 through 32 only when XLEN=32.

Availability And Extension Conditions

Base Conditions

RV32
Zicntr depends on Zicsr

Single-Instruction Or Standard Form

cycle bits 63 through 32

Fallback / Boundary

rdcycleh exists only when XLEN=32.

Notes

A high-low-high comparison retry obtains a valid 64-bit cycle value.

How To Read The Expansion

Step 1

CSRRS with rs1=x0 reads cycle bits 63 through 32 on RV32; this canonical form does not write the CSR.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 30 Table 6

RISC-V Unprivileged ISA Manual 2026-01-20, Section 7.1

When To Think Of It First

Read the high half in the RV32 cycle high-low-high comparison retry sequence

Pitfalls / Common Confusions

rdcycleh exists only when XLEN=32; do not present it as an RV64 read form.

A high-half read alone does not provide a full 64-bit value. The manual's safe-read example reads high, low, then high again and retries if the high-half values differ.

Zicntr depends on Zicsr, and some execution environments may prohibit counter access.

FAQ

Is rdcycleh a real RISC-V instruction?

rdcycleh is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using rdcycleh?

rdcycleh exists only on RV32; a full read compares high, low, high and retries on mismatch.