negw

RISC-V negw Pseudo-Instruction Details

Assembler pseudo-instruction

RV64 word-negate pseudo-instruction, expanding to subw rd, x0, rs. It negates only the low 32 bits in two’s-complement arithmetic and sign-extends the 32-bit result to XLEN.

What You Write

negw rd, rs

Typical Real Expansion

subw rd, x0, rs

What This Pseudo Instruction Is Saving You From Writing

RV64 has both XLEN-wide and word operations; negw makes the common C/ABI 32-bit integer negation semantics explicit.

negw primarily means "RV64 negate low 32 bits". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats negw as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of SUBW and the other expanded instructions, not from a separate negw hardware opcode.

Availability And Extension Conditions

Base Conditions

RV64I word-instruction semantics

Single-Instruction Or Standard Form

RV64 uses SUBW rd, x0, rs

Fallback / Boundary

On RV32, ordinary neg/sub already covers the XLEN width.

Notes

The result is computed in the low 32 bits and sign-extended; original upper bits are not preserved.

How To Read The Expansion

Step 1

SUBW subtracts rs from x0, producing a 32-bit negated result sign-extended to XLEN.

What You May See In objdump / Disassembly

Disassembly may show either the pseudo-instruction or the expanded real instruction, depending on tool options and context.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Negate a 32-bit integer on RV64

Implement sign flip for C int values

Preserve the 32-bit sign-extension semantics of word instructions

Pitfalls / Common Confusions

Applies to RV64 word-instruction semantics; on RV32 ordinary neg already covers XLEN width

The result is sign-extended from 32 bits; high 32 bits are not preserved

Negating the minimum 32-bit negative value still wraps in two’s-complement arithmetic

FAQ

Is negw a real RISC-V instruction?

negw is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using negw?