negw

RISC-V negw Pseudo-Instruction Details

Assembler pseudo-instruction

RISC-V negw is an RV64 assembler pseudo-instruction that expands to subw rd, x0, rs. SUBW subtracts in the low 32 bits, then sign-extends the 32-bit result to XLEN.

What You Write

negw rd, rs

Typical Real Expansion

subw rd, x0, rs

What This Pseudo Instruction Is Saving You From Writing

The assembly manual lists negw as the standard pseudo-instruction spelling for subw rd, x0, rs, with a two's-complement word meaning.

Availability And Extension Conditions

Base Conditions

RV64I

Single-Instruction Or Standard Form

SUBW rd, x0, rs

Fallback / Boundary

negw is not an RV32I instruction.

Notes

The result is computed in the low 32 bits and sign-extended; original upper bits are not preserved.

How To Read The Expansion

Step 1

SUBW subtracts rs from x0, producing a 32-bit negated result sign-extended to XLEN.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 29 Table 5

RISC-V Unprivileged ISA Manual 2026-01-20, Section 4.2.2

FAQ

Is negw a real RISC-V instruction?

negw is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using negw?

negw applies only to RV64I; its low-32-bit result is sign-extended to XLEN.