zext.w

RISC-V zext.w Pseudo-Instruction Details

Assembler pseudo-instruction

The RISC-V zext.w pseudo-instruction expands to slli rd, rs, XLEN - 32 then srli rd, rd, XLEN - 32 to zero-extend a word. On RV64 with Zba available, the table has a single-instruction form.

What You Write

zext.w rd, rs

Typical Real Expansion

slli rd, rs, XLEN - 32 srli rd, rd, XLEN - 32

What This Pseudo Instruction Is Saving You From Writing

The assembly manual provides the zext.w zero-extend-word spelling for this two-shift sequence.

The RISC-V zext.w pseudo-instruction uses an SLLI/SRLI sequence to zero-extend low 32 bits; on RV64 with Zba, ADD.UW provides one instruction.

Official Semantics Checklist

the RISC-V Assembly Programmer's Manual lists the zext.w rd, rs SLLI/SRLI expansion and notes one instruction when Zba is available.

Unprivileged ISA Section 2.4.1 defines SLLI with lower zeros and SRLI with upper zeros.

The Unprivileged ISA Zba table lists ADD.UW for RV64, and Section 30.9.1 lists zext.w rd, rs1 as add.uw rd, rs1, zero.

Availability And Extension Conditions

Base Conditions

Two SLLI/SRLI shifts

Single-Instruction Or Standard Form

On RV64 with Zba, ADD.UW provides one instruction.

Fallback / Boundary

Use the table's SLLI/SRLI sequence.

Notes

Zero-extends the low 32 bits.

How To Read The Expansion

Step 1

SLLI shifts left logically with zeros shifted into lower bits.

Step 2

SRLI shifts right logically with zeros shifted into upper bits.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 29 Table 5

RISC-V Unprivileged ISA Manual 20260120, Section 2.4.1

RISC-V Unprivileged ISA Manual 20260120, Sections 30.2 and 30.9.1

When To Think Of It First

Use zext.w for the table's low-32-bit zero-extension operation.

Pitfalls / Common Confusions

The base expansion has two shifts; the single-instruction form requires RV64 and Zba.

The table gives a shift amount of XLEN - 32, which is 32 on RV64.

FAQ

What is the base zext.w expansion?

The Assembly Manual lists slli rd, rs, XLEN - 32 followed by srli rd, rd, XLEN - 32.