zext-w

RISC-V zext-w Pseudo-Instruction Details

Assembler pseudo-instruction

RV64 zero-extend-word pseudo-instruction that keeps the low 32 bits and clears the high bits. Without Zba it can use an slli/srli sequence; with Zba it can use add.uw.

What You Write

zext.w rd, rs

Typical Real Expansion

# RV64+Zba path add.uw rd, rs, x0 # or RV64 without Zba: slli rd, rs, 32 srli rd, rd, 32

What This Pseudo Instruction Is Saving You From Writing

On RV64, 32-bit unsigned values need the high 32 bits cleared; zext.w expresses that intent and lets the toolchain choose add.uw or a shift sequence based on Zba availability.

zext-w primarily means "RV64 zero-extend low 32 bits". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats zext-w as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of ADD.UW and the other expanded instructions, not from a separate zext-w hardware opcode.

Availability And Extension Conditions

Base Conditions

Mainly for RV64

Single-Instruction Or Standard Form

Zba provides the ADD.UW path

Fallback / Boundary

On RV64 without Zba, SLLI 32 followed by SRLI 32 can clear the upper 32 bits.

Notes

On RV32, 32-bit zero extension does not have the same meaning because XLEN is already 32.

Toolchain And Linker Boundaries

zext.w mainly targets RV64; with Zba it can use add.uw, while a base RV64 path can use SLLI/SRLI.

Whether final output shows add.uw or a shift sequence depends on target extensions and assembler/disassembler choices.

How To Read The Expansion

Step 1

Zba path: ADD.UW zero-extends the low 32 bits of rs into rd; x0 as the second operand leaves the value unchanged.

Step 2

Base RV64 without Zba step 1: SLLI shifts left by 32 bits, discarding the original upper 32 bits.

Step 3

Base RV64 without Zba step 2: SRLI shifts right logically by 32 bits, filling upper bits with zeros.

What You May See In objdump / Disassembly

Disassemblers may show add.uw rd,rs,x0 or an equivalent shift sequence as zext.w rd,rs.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Normalize a 32-bit unsigned integer to XLEN on RV64

Clear stale data in the high 32 bits of a register

Compare with sext.w to understand 32-bit zero versus sign extension

Pitfalls / Common Confusions

Only meaningful when XLEN is greater than 32, mainly RV64

The available expansion depends on Zba support

Do not confuse with sext.w; zext.w clears high 32 bits while sext.w fills them from bit31

FAQ

Is zext-w a real RISC-V instruction?

zext-w is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using zext-w?