Does add.uw access memory?
No. It reads integer register operands and writes rd only.
ADD.UW
RISC-V ADD.UW Instruction Details
Instruction ManualOP-32 (R-type)Add unsigned word: zero-extend lower word of rs1 and add to rs2 (RV64)
Instruction Syntax
add.uw rd, rs1, rs2
Operand Breakdown
This is a OP-32 (R-type)-format instruction. Confirm operand positions based on the assembly syntax.
ZbaAddress Generation
Related Search Terms
Instruction Behavior
add.uw is an RV64 Zba instruction. It zero-extends the low 32 bits of rs1, adds that value to rs2 using XLEN-width addition, and writes rd.
ADD.UW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
add.uw
,
,
Execution Context
t1(x6)
0x0000000000000014
a0(x10)
0x0000000000001000
31..25
24..20
19..15
14..12
11..7
6..0
0000100
funct7
01010
rs2
00110
rs1
000
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x08A302BB
opcode
0111011 -> OP-32
funct3
000 -> ADD.UW
funct7
0000100 -> ADD.UW selector
rd / rs1 / rs2
t0(x5) / t1(x6)=0x0000000000000014 / a0(x10)=0x0000000000001000
rs1[31:0]
0x00000014 -> zero-extend = 0x0000000000000014
RV64 XLEN-wide add
0x0000000000001000 + 0x0000000000000014 = 0x0000000000001014
x5
t0(x5) = 0x0000000000001014
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x08A302BB
syntax : add.uw t0(x5), t1(x6), a0(x10)
result : t0(x5) = 0x0000000000001014
Architectural Result
t0(x5) = 0x0000000000001014
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
add.uw is commonly used for RV64 address generation: zero-extend rs1[31:0], then add rs2.
These instructions are part of a B-extension subset and operate on XLEN-wide integer register values.
It is a Zba address-generation bit-manipulation instruction, not ordinary ADDW; the result is not sign-extended from 32 bits.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «add.uw x10, x11, x12».
Basic Arithmetic
Understand this scenario with real code like «add.uw x10, x11, x12».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OP-32 (R-type).
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
RV64 only; RV32 does not include this instruction.
Only the low 32 bits of rs1 are zero-extended; rs2 participates as an XLEN-wide addend.
add.uw rd, rs1, x0 can zero-extend a 32-bit word, but addiw has sign-extension semantics.
FAQ
How is add.uw different from addw?
add.uw zero-extends rs1[31:0] and performs an XLEN add with rs2; addw performs a 32-bit add and sign-extends bit 31 to XLEN.