Does add.uw access memory?
No. It reads integer register operands and writes rd only.
ADD.UW
RISC-V ADD.UW Instruction Details
Instruction ManualR-typeAdd unsigned word: zero-extend lower word of rs1 and add to rs2 (RV64)
Instruction Syntax
add.uw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbaAddress Generation
Related Search Terms
Instruction Behavior
add.uw is an RV64 Zba instruction. It zero-extends the low 32 bits of rs1, adds that value to rs2 using XLEN-width addition, and writes rd.
Quick Understanding & Search Notes
add.uw is commonly used for RV64 address generation: zero-extend rs1[31:0], then add rs2.
These instructions are part of a B-extension subset and operate on XLEN-wide integer register values.
It is a Zba address-generation bit-manipulation instruction, not ordinary ADDW; the result is not sign-extended from 32 bits.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «add.uw x10, x11, x12».
Basic Arithmetic
Understand this scenario with real code like «add.uw x10, x11, x12».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
RV64 only; RV32 does not include this instruction.
Only the low 32 bits of rs1 are zero-extended; rs2 participates as an XLEN-wide addend.
add.uw rd, rs1, x0 can zero-extend a 32-bit word, but addiw has sign-extension semantics.
FAQ
How is add.uw different from addw?
add.uw zero-extends rs1[31:0] and performs an XLEN add with rs2; addw performs a 32-bit add and sign-extends bit 31 to XLEN.