How is add.uw different from addw?
add.uw zero-extends rs1[31:0] and performs an XLEN add with rs2; addw performs a 32-bit add and sign-extends bit 31 to XLEN.
ADD.UW
RISC-V ADD.UW Instruction Details
Instruction ManualOP-32 (R-type)Add unsigned word: zero-extend lower word of rs1 and add to rs2 (RV64)
Instruction Syntax
add.uw rd, rs1, rs2
rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
Zero-extend rs1[31:0]; rs2 supplies all 64 bits.
Requires RV64 Zba; keep the low 64 sum bits, without word-result sign extension.
ZbaAddress Generation
Related Search Terms
Instruction Behavior
RV64 Zba: zero-extend rs1[31:0], add rs2 at 64-bit width, and write rd.
ADD.UW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
add.uw
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x0000000000000014
a0(x10)
0x0000000000001000
31..25
24..20
19..15
14..12
11..7
6..0
0000100
funct7
01010
rs2
00110
rs1
000
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x08A302BB
opcode
0111011 -> OP-32
funct3
000 -> ADD.UW
funct7
0000100 -> ADD.UW selector
rd / rs1 / rs2
t0(x5) / t1(x6)=0x0000000000000014 / a0(x10)=0x0000000000001000
rs1[31:0]
0x00000014 -> zero-extend = 0x0000000000000014
RV64 XLEN-wide add
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x08A302BB
syntax : add.uw t0(x5), t1(x6), a0(x10)
Pending result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
add.uw is commonly used for RV64 address generation: zero-extend rs1[31:0], then add rs2.
RV64 Zba: zero-extend rs1[31:0]; rs2 supplies all 64 bits.
It is a Zba address-generation bit-manipulation instruction, not ordinary ADDW; the result is not sign-extended from 32 bits.
Common Usage Scenarios
Address & Pointer
RV64 Zba, x11=0xffffffff80000000 and x12=1: zero-extend the low word of x11, then add; x10=0x0000000080000001.
Basic Arithmetic
RV64 Zba, x11=0xffffffff80000000 and x12=1: zero-extend the low word of x11, then add; x10=0x0000000080000001.
Pre-Use Checklist
Syntax Check
- rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
- Zero-extend rs1[31:0]; rs2 supplies all 64 bits.
Semantic Check
- Requires RV64 Zba; keep the low 64 sum bits, without word-result sign extension.
Pitfalls / Common Confusions
RV64 only; RV32 does not include this instruction.
Only the low 32 bits of rs1 are zero-extended; rs2 participates as an XLEN-wide addend.
add.uw rd, rs1, x0 can zero-extend a 32-bit word, but addiw has sign-extension semantics.