Does SLLI.UW access memory?
No. It operates only on integer registers.
SLLI.UW
RISC-V SLLI.UW Instruction Details
Instruction ManualI-typeShift left unsigned word by immediate (RV64)
Instruction Syntax
slli.uw rd, rs1, shamt
rd and rs1 select integer registers x0–x31; shamt is an unsigned 6-bit shift amount in 0–63.
32-bit OP-IMM-32: opcode=0011011, funct3=001; bits31:26 are fixed to 000010, bits25:20 encode shamt, and rs1/rd occupy bits19:15/11:7.
RV64 Zba only: zero-extend rs1[31:0] before shifting left by shamt. Keep the low 64 bits without 32-bit sign extension.
When rs1=rd, read the old source. x0 supplies zero and writes to it are discarded. No data-memory access occurs.
ZbaAddress Generation
Instruction Behavior
Zero-extends rs1[31:0], then logically shifts left by an immediate from 0 to 63, keeping the low 64 bits. Equivalent to SLLI after zext.w on rs1; RV64 Zba only.
SLLI.UW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
slli.uw
,
,
Execution Context
Assumes Zba is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
a6(x16)
0xFFFFFFFFFFFFFFF0
31..26
25
24..20
19..15
14..12
11..7
6..0
000010
fixed imm[11:6]
0
shamt[5]
00011
shamt[4:0]
10000
rs1
001
funct3
00101
rd
0011011
opcode
Execution Data Path
instruction
0x0838129B
opcode
0011011 -> OP-IMM-32
funct3
001 -> SLLI.UW
imm[11:6] / bit25
imm[11:6]=000010 fixed; bit25=shamt[5]=0
rd / rs1
t0(x5) / a6(x16)[31:0]=0xFFFFFFF0
fixed imm[11:6] + shamt[5:0]
imm[11:6]=000010 fixed; shamt[5:0]=000011
zero-extend and shift
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x0838129B
syntax : slli.uw t0(x5), a6(x16), 3
Result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SLLI.UW is an RV64 Zba instruction: it zero-extends rs1[31:0], shifts by shamt[5:0], and writes the XLEN-wide result to rd.
It extracts and zero-extends the low 32 bits of rs1, then shifts left by the immediate.
It is an RV64 Zba instruction useful for unsigned 32-bit index expansion; do not treat it as sign-extension followed by a shift.
Common Usage Scenarios
Unsigned word zero-extension and left shift
RV64 Zba, x11=0xffffffff80000001: slli.uw x10, x11, 4 zero-extends the low word first and writes x10=0x0000000800000010.
Address calculation
RV64 Zba, x11=0xffffffff80000001: slli.uw x10, x11, 4 zero-extends the low word first and writes x10=0x0000000800000010.
Pre-Use Checklist
Syntax Check
- rd and rs1 select integer registers x0–x31; shamt is an unsigned 6-bit shift amount in 0–63.
- 32-bit OP-IMM-32: opcode=0011011, funct3=001; bits31:26 are fixed to 000010, bits25:20 encode shamt, and rs1/rd occupy bits19:15/11:7.
Semantic Check
- RV64 Zba only: zero-extend rs1[31:0] before shifting left by shamt. Keep the low 64 bits without 32-bit sign extension.
- When rs1=rd, read the old source. x0 supplies zero and writes to it are discarded. No data-memory access occurs.
Pitfalls / Common Confusions
RV64 only
shamt range 0-63
FAQ
What is the result width of SLLI.UW?
rs1[31:0] is first zero-extended to XLEN, then shifted left by shamt[5:0]; the XLEN-wide result is written to rd.