Does SLLI.UW access memory?
No. It operates only on integer registers.
SLLI.UW
RISC-V SLLI.UW Instruction Details
Instruction ManualI-typeShift left unsigned word by immediate (RV64)
Instruction Syntax
slli.uw rd, rs1, shamt
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZbaAddress Generation
Instruction Behavior
Zero-extends rs1[31:0] and logically shifts it left by shamt[5:0]. It is equivalent to applying zext.w to rs1 before SLLI, not to ADD.UW followed by SLLI. It is an RV64 Zba instruction.
SLLI.UW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
slli.uw
,
,
Execution Context
a6(x16)
0xFFFFFFFFFFFFFFF0
31..26
25
24..20
19..15
14..12
11..7
6..0
000010
fixed imm[11:6]
0
shamt[5]
00011
shamt[4:0]
10000
rs1
001
funct3
00101
rd
0011011
opcode
Execution Data Path
instruction
0x0838129B
opcode
0011011 -> OP-IMM-32
funct3
001 -> SLLI.UW
imm[11:6] / bit25
imm[11:6]=000010 fixed; bit25=shamt[5]=0
rd / rs1
t0(x5) / a6(x16)[31:0]=0xFFFFFFF0
fixed imm[11:6] + shamt[5:0]
imm[11:6]=000010 fixed; shamt[5:0]=000011
zero-extend and shift
EXTZ(0xFFFFFFF0) << 3 = 0x00000007FFFFFF80
x5
t0(x5) = 0x00000007FFFFFF80
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x0838129B
syntax : slli.uw t0(x5), a6(x16), 3
result : t0(x5) = 0x00000007FFFFFF80
Architectural Result
t0(x5) = 0x00000007FFFFFF80
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SLLI.UW is an RV64 Zba instruction: it zero-extends rs1[31:0], shifts by shamt[5:0], and writes the XLEN-wide result to rd.
It extracts and zero-extends the low 32 bits of rs1, then shifts left by the immediate.
It is an RV64 Zba instruction useful for unsigned 32-bit index expansion; do not treat it as sign-extension followed by a shift.
Common Usage Scenarios
Shift & Rotate
Understand this scenario with real code like «slli.uw x10, x11, 4 ; x10 = zero_ext(x11[31:0]) << 4».
Type Conversion
Understand this scenario with real code like «slli.uw x10, x11, 4 ; x10 = zero_ext(x11[31:0]) << 4».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
RV64 only
shamt range 0-63
FAQ
What is the result width of SLLI.UW?
rs1[31:0] is first zero-extended to XLEN, then shifted left by shamt[5:0]; the XLEN-wide result is written to rd.