Does SH1ADD.UW access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
SH1ADD.UW
RISC-V SH1ADD.UW Instruction Details
Instruction ManualR-typeShift unsigned word left by 1 and add (RV64)
Instruction Syntax
sh1add.uw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbaAddress Generation
Instruction Behavior
Zero-extends lower 32 bits of rs1 as unsigned word, shifts left by 1, adds rs2. For unsigned word-indexed array address generation. Part of Zba.
Quick Understanding & Search Notes
SH1ADD.UW is a B/Zba instruction for zero-extend low word, shift left 1, and add. This page is checked against the official B extension semantics, with emphasis on XLEN, W suffixes, .uw suffixes, and bitwise or rotate boundaries.
The low 32 bits of rs1 are zero-extended, shifted left by 1, and added to rs2.
The .uw form is an RV64 address-generation instruction; apart from unsigned-word extraction from rs1, the addition is XLEN-wide.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «sh1add.uw x10, x11, x12 ; x10 = x12 + (zero_ext(x11[31:0]) << 1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
RV64 only
FAQ
What is the result width of SH1ADD.UW?
Except that W-suffixed forms produce a 32-bit result then sign-extend and .uw forms first extract a 32-bit unsigned operand, the result is written to rd at XLEN width.