Does SH1ADD access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
SH1ADD
RISC-V SH1ADD Instruction Details
Instruction ManualR-typeShift left by 1 and add
Instruction Syntax
sh1add rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbaAddress GenerationBit Manipulation
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
SH1ADD uses opcode 0110011 (0x33), funct3 010, funct7 0010000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 010 (0x2)
funct7: 0010000 (0x10)
Instruction Behavior
Shifts rs1 left by 1 then adds rs2: rd = rs2 + (rs1 << 1). For halfword (2-byte) array address generation. Part of Zba.
Quick Understanding & Search Notes
SH1ADD is a B/Zba instruction for rs2 plus rs1 shifted left by 1. This page is checked against the official B extension semantics, with emphasis on XLEN, W suffixes, .uw suffixes, and bitwise or rotate boundaries.
rs1 is shifted left by 1 and added to rs2, commonly for address generation.
The addition is XLEN-wide; the instruction itself does not access memory.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «sh1add x10, x11, x12 ; x10 = x12 + (x11 << 1)».
Multiplication & Division
Understand this scenario with real code like «sh1add x10, x11, x12 ; x10 = x12 + (x11 << 1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Shift amount is fixed at 1
FAQ
What is the result width of SH1ADD?
Except that W-suffixed forms produce a 32-bit result then sign-extend and .uw forms first extract a 32-bit unsigned operand, the result is written to rd at XLEN width.