Does SH1ADD access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
SH1ADD
RISC-V SH1ADD Instruction Details
Instruction ManualR-typeShift left by 1 and add
Instruction Syntax
sh1add rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZbaAddress GenerationBit Manipulation
Instruction Behavior
Shifts rs1 left by 1 then adds rs2: rd = rs2 + (rs1 << 1). For halfword (2-byte) array address generation. Part of Zba.
SH1ADD Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sh1add
,
,
Execution Context
t1(x6)
0x00000014
a0(x10)
0x00001000
31..25
24..20
19..15
14..12
11..7
6..0
0010000
funct7
01010
rs2
00110
rs1
010
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x20A322B3
opcode
0110011 -> OP
funct3
010 -> SH1ADD
funct7
0010000 -> SH1ADD selector
rd / rs1 / rs2
t0(x5) / t1(x6)=0x00000014 / a0(x10)=0x00001000
shift and add
0x00000014 << 1 = 0x00000028; 0x00001000 + 0x00000028 = 0x00001028
x5
t0(x5) = 0x00001028
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x20A322B3
syntax : sh1add t0(x5), t1(x6), a0(x10)
result : t0(x5) = 0x00001028
Architectural Result
t0(x5) = 0x00001028
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SH1ADD is a Zba instruction: it shifts rs1 left by 1, adds rs2, and writes the XLEN-wide result to rd.
rs1 is shifted left by 1 and added to rs2, commonly for address generation.
The addition is XLEN-wide; the instruction itself does not access memory.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «sh1add x10, x11, x12 ; x10 = x12 + (x11 << 1)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Shift amount is fixed at 1
FAQ
What is the result width of SH1ADD?
This instruction performs the shift and addition at XLEN width and writes the XLEN-wide result to rd.